SCSI Registers
5-69
GEN
General Purpose Timer Expired
1
Setting this bit allows the SYM53C895 to generate an
interrupt when the general purpose timer has expired.
The time measured is the time between enabling and
disabling of the timer. See the description of the SCSI
Timer One (STIME1) register (bits [3:0]) on
page 5-77 for
more information on the general purpose timer.
HTH
Handshake to Handshake Timer Expired
0
Setting this bit allows the SYM53C895 to generate an
interrupt when the handshake to handshake timer has
expired. The time measured is the SCSI Request to
Request (target) or Acknowledge to Acknowledge
(initiator) period. See the description of the STIME0
register, bits [7:4], for more information on the handshake
to handshake timer.
Register: 0x42
SCSI Interrupt Status Zero (SIST0)
Read Only
Reading the SIST0 register returns the status of the various interrupt
conditions, whether they are enabled in the SIEN0 register or not. Each
bit set indicates that the corresponding condition has occurred. Reading
the SIST0 clears the interrupt status.
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register because additional
interrupts may be pending (the SYM53C895 stacks interrupts). SCSI
interrupt conditions may be individually masked through the SCSI
Interrupt Enable Zero (SIEN0) register.
When performing consecutive 8-bit reads of the DSTAT, SIST0, and
SIST1 registers (in any order), insert a delay equivalent to 12 CLK
periods between the reads to ensure the interrupts clear properly. Also,
if reading the registers when both the Interrupt Status (ISTAT) SIP and
DIP bits may not be set, the SCSI Interrupt Status Zero (SIST0) and
SCSI Interrupt Status One (SIST1) registers should be read before the
DMA Status (DSTAT) register to avoid missing a SCSI interrupt. For more
76543210
M/A
CMP
SEL
RSL
SGE
UDC
RST
PAR
00000000