5-24
Registers
register during a send operation. This byte is combined
with the rst byte from the subsequent transfer so that a
wide transfer can be completed.
For more information, see the “Chained Mode” section in
Chapter 2, “Functional Description.”
SLPMD
SLPAR Mode Bit
5
If this bit is clear, the SCSI Longitudinal Parity (SLPAR)
register functions like the SYM53C825. If this bit is set,
the SLPAR register reects the high or low byte of the
SLPAR word, depending on the state of SCNTL2 bit 4. It
also allows a seed value to be written to the SLPAR
register.
SLPHBEN
SLPAR High Byte Enable
4
If this bit is clear, the low byte of the SLPAR word is
accessible through the SLPAR register. If this bit is set,
the high byte of the SLPAR word is present in the SLPAR
register.
WSS
Wide SCSI Send
3
When read, this bit returns the value of the Wide SCSI
Send (WSS) ag. Asserting this bit clears the WSS ag.
This clearing function is self-clearing.
When the WSS ag is high following a wide SCSI send
operation, the SCSI core is holding a byte of “chain” data
in the SCSI Output Data Latch (SODL) register. This data
becomes the rst low-order byte sent when married with
a high-order byte during a subsequent data send transfer.
Performing a SCSI receive operation clears this bit. Also,
performing any non-wide transfer clears this bit.
VUE0
Vendor Unique Enhancements bit 0
2
This bit is a read only value indicating whether the group
code eld in the SCSI instruction is standard or vendor
unique. If reset, the bit indicates standard group codes. If
set, the bit indicates vendor unique group codes. The
value in this bit is reloaded at the beginning of all
asynchronous target receives. The default for this bit is
reset.
VUE1
Vendor Unique Enhancements bit 1
1
This bit disables the automatic byte count reload during
Block Move instructions in the command phase. If this bit