
Draft xx/xx/xx
4-18
Signal Descriptions
Rev. letter
Copyright 1999 by LSI Logic Corporation. All rights reserved.
Table 4.12
External Memory Interface Pins
Symbol
Pin No.
Ball No.
Type
Description
MAS0/
186
M2
O
Memory Address Strobe 0. This pin latches in the least
signicant address byte of an external EEPROM or ash
memory. Since the SYM53C895 moves addresses eight bits
at a time, this pin connects to the clock of an external bank of
ip-ops that assemble up to a 20-bit address for the external
memory.
MAS/1
185
M1
O
Memory Address Strobe 1. This pin latches in the address
byte corresponding to address bits [15:8] of an external
EEPROM or ash memory. Since the SYM53C895 moves
addresses eight bits at a time, this pin connects to the clock
of an external bank of ip-ops that assemble up to a 20-bit
address for the external memory.
MAD[7:0]
See individual
pin
descriptions
The MAD[7:0] pins form the memory address/data bus. This
bus is used in conjunction with the memory address strobe
pins and external address latches to assemble up to a 20-bit
address for an external EEPROM or ash memory. This bus
puts out the most signicant byte rst and nishes with the
least signicant byte. It also writes data to a ash memory or
read data into the chip from external EEPROM or ash
memory. The eight signals on the MAD bus have specic
functions. Refer to the individual pin descriptions below.
MAD[7:6]
69–70
N19, N20
I/O
MAD[7:6] enable different power-up options related to the
external serial EEPROM interface. These options are
programmed by connecting a 4.7 K
resistor between the
appropriate MAD pin and VSS. For more information, refer to
the Serial EEPROM Interface section in
Chapter 2 and the
Subsystem ID/Subsystem Vendor ID register descriptions in
00
Vendor specic information is automatically
downloaded from the serial EEPROM through
GPIO0 (clock) and GPIO1 (data) and loaded
into PCI conguration registers 0x2C–0x2F
01
Reserved
10
No download is performed, however, the PCI
conguration registers 0x2C–0x2F are now
writable.
11
Vendor-specic information is automatically
downloaded from the EEPROM through
GPIO0 (data) and GPIO1 (clock) and loaded
into PCI conguration registers 0x2C–0x2F.