
SCSI Timings
7-63
Figure 7.37 SYM53C895 Pin Diagram, 208-pin QFP
NC
AD26
AD25
VSS-PCI
AD22
AD19
AD17
VSS-PCI
IRDY/
DEVSEL/
STOP/
PERR/
AD14
AD12
AD11
AD10
VSS-PCI
AD8
C_BE0/
VDD-PCI
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
36
37
38
39
40
42
44
46
48
50
AD21
AD20
VSS-PCI
AD15
AD7
AD6
AD4
V5BIAS(PCI)
NC
52
AD2
SYM53C895
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
41
43
45
47
49
51
VDD-PCI
V5BIAS(PCI)
C_BE3/
AD23
VDD-PCI
AD18
FRAME/
VDD-PCI
PAR
C_BE1/
VDD-PCI
AD24
IDSEL
AD16
C_BE2/
TRDY/
SERR/
AD13
AD9
AD5
AD3
NC
SD1-
SD3+
SD4-
SD5-
VSS-SCSI
SD7-
SDP0-
RBIAS+
RBIAS-
SBSY-
VSS-SCSI
SRST+
SRST-
SMSG-
VDD-SCSI
SSEL+
SCD-
156
154
152
150
148
146
144
142
140
138
136
134
132
130
128
126
124
122
121
120
119
118
117
115
113
111
109
107
SD3-
SD4+
SATN-
SBSY+
SSEL-
SCD+
NC
105
NC
155
153
151
149
147
145
143
141
139
137
135
133
131
129
127
125
123
116
114
112
110
108
106
NC
SD1+
SD2-
VDD-SCSI
SD5+
SD7+
VDD-SCSI
VSS-SCSI
SATN+
VDD-SCSI
SACK-
VSS-SCSI
SD2+
SD6+
SD6-
SDP0+
VSS-SCSI
SACK+
SMSG+
VSS-SCSI
NC
AD1
VDD-PCI
GPIO1_MASTER/
GPIO4
MAD7
MAD6
MAD3
MAD0
MA
C/_TEST
OUT
SCLK
VDD-SCSI
SD10-
SD10+
VSS-SCSI
SD9+
SD8-
SD8+
SIO+
VDD-CORE
GPIO3
VSS-A
VDD-A
VDD-SCSI
SIO-
SREQ+
NC
VSS-PCI
IRQ/
V5BIAS(MEM)
GPIO2
VSS-CORE
VDD-IO
MAD2
VSS-IO
TEST
DIFFSENS
SD11+
AD0
GPICO_FETCH/
MAD5
MAD4
MAD1
VDD-IO
SD11-
SD9-
SREQ-
NC
VDD-SCSI
SD15-
SD14+
SD13+
VDD-SCSI
TESTIN
TEST
VDD-IO
VDD-CORE
VSS-PCI
RST/
CLK
VDD-PCI
REQ/
AD31
AD29
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
192
193
194
195
196
198
200
202
204
206
SD15+
SD14-
VSS-CORE
MOE/
VSS-PCI
AD30
AD27
NC
208
NC
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
197
199
201
203
205
207
NC
SD0+
SDP1+
VSS-SCSI
SD13-
TEST
VSS-IO
TEST
MAS0/
MWE/
BIG_LIT/
SD0-
SDP1-
SD12-
SD12+
TEST
MAS1/
MCE/
GNT/
AD28
NC
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
88
89
90
91
92
94
96
98
100
102
104
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
93
95
97
99
101
103
1. The decoupling capacitor arrangement shown above is recommended to maximize the benets of the
internal split ground system. Capacitor values between 0.01 and 0.1
F should provide adequate noise
isolation. Because of the number of high current drivers on the SYM53C895, a multilayer PC board with
power and ground planes is required.
2. A 2.2 k
resistor is required between RBIAS+ and RBIAS pins. RBIAS must be connected to 3.3 V as
well.
208-Pin
Quad Flat Pack