
2-8
Functional Description
2.3.1 Internal SCRIPTS RAM
The SYM53C895 has 4 Kbytes (1024 x 32 bits) of internal, general
purpose RAM. The RAM is designed for SCRIPTS program storage, but
is not limited to this type of information. When the chip fetches SCRIPTS
instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the PCI bus. Other
types of access to the RAM by the SYM53C895 use the PCI bus as if
they were external accesses. The MAD5 pin enables the 4 Kbytes
internal RAM, when it is connected to VDD through a 4.7 K resistor. To
disable the internal RAM, connect a 4.7 K
resistor between the MAD5
pin and VSS.
The PCI system BIOS can relocate the RAM anywhere in a 32-bit
address space. The RAM Base Address register in PCI conguration
space contains the base address of the internal RAM. This register is
similar to the ROM Base Address register in PCI conguration space. To
simplify loading of SCRIPTS instructions, the base address of the RAM
appears in the SCRATCHB register when bit 3 of the CTEST2 register
is set. The RAM is byte-accessible from the PCI bus and is visible to any
bus-mastering device on the bus. External accesses to the RAM (that is,
by the CPU) follow the same timing sequence as a standard slave
register access, except that the target wait states required drops from
5to 3.
A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
2.4 Prefetching SCRIPTS Instructions
To enable the prefetch logic, set the Prefetch Enable bit in the DCNTL
register. After doing so, the prefetch logic in the SYM53C895 fetches
8 dwords of instructions. The prefetch logic automatically determines the
maximum burst size that it can perform, based on the burst length as
determined by the values in the DMODE register. If the burst size is less
than four dwords, the SYM53C895 performs normal instruction fetches.
While the SYM53C895 is prefetching SCRIPTS instructions, the PCI