
SCSI Registers
5-73
Register:
0x44
SCSI Longitudinal Parity (SLPAR)
Read/Write
The SLPAR register consists of two multiplexed bytes; other register bit
settings determine what is displayed at this memory location at any given
time. When bit 5 in the SCSI Control Two (SCNTL2) (SLPMD) register is
cleared, the chip XORs the high and low bytes of the SLPAR register
together to give a single-byte value which is displayed in the SLPAR
register. If the SLPMD bit is set, then the SLPAR register shows either
the high byte or the low byte of the SLPAR word. The SLPAR High Byte
Enable bit, SCNTL2 bit 4, determines which byte of the SLPAR register
is visible on the SLPAR register at any given time. If this bit is cleared,
the SLPAR register contains the low byte of the SLPAR word. If it is set,
the SLPAR register contains the high byte of the SLPAR word.
This register performs a bytewise longitudinal parity check on all SCSI
data received or sent through the SCSI core. If one of the bytes received
or sent (usually the last) is the set of correct even parity bits, SLPAR
should go to zero (assuming it started at zero). As an example, suppose
that the following three data bytes and one check byte are received from
the SCSI bus (all signals are shown active high):
A one in any bit position of the nal SLPAR value would indicate a
transmission error.
The SLPAR register can also be used to generate the check bytes for
SCSI send operations. If the SLPAR register contains all zeros prior to
sending a block move, it will contain the appropriate check byte at the
end of the block move. This byte must then be sent across the SCSI bus.
Note:
Writing any value to this register resets it to zero.
Data Bytes
Running SLPAR
---
00000000
1. 11001100
11001100 (XOR of word 1)
2. 01010101
10011001 (XOR of word 1 and 2)
3. 00001111
10010110 (XOR of word 1, 2 and 3) Even Parity
>>>10010110
4. 10010110
00000000