PCI Cache Mode
3-7
multiple cache line size transfers are not desired, the DMODE burst size
can be set to exactly the cache line size and the chip only issues single
cache line transfers.
After each data transfer, the chip re-evaluates the burst size based on
the amount of remaining data to transfer and again selects the highest
possible multiple of the cache line size, no larger than the DMODE burst
size. The most likely scenario of this scheme is that the chip selects the
DMODE burst size after alignment, and issues bursts of this size. The
burst size, in effect, throttles down toward the end of a long Memory
Move or Block Move transfer until only the cache line size burst size is
left. The chip nishes the transfer with this burst size.
3.3.5.2 Latency
In accordance with the PCI specication, the chip's latency timer is
ignored when issuing a Memory Write and Invalidate command such that
when a latency time-out has occurred, the SYM53C895 continues to
transfer up until a cache line boundary is reached. At that point, the chip
relinquishes the bus and nishes the transfer at a later time using
another bus ownership. If the chip is transferring multiple cache lines it
continues to transfer until the next cache boundary is reached.
3.3.5.3 PCI Target Retry
During a Write and Invalidate transfer, if the target device issues a retry
(STOP with no TRDY, indicating that no data was transferred), the
SYM53C895 relinquishes the bus and immediately tries to nish the
transfer on another bus ownership. The chip issues another Memory
Write and Invalidate command on the next ownership in accordance with
the PCI specication.
3.3.5.4 PCI Target Disconnect
During a Write and Invalidate transfer, if the target device issues a
disconnect the SYM53C895 relinquishes the bus and immediately tries
to nish the transfer on another bus ownership. The chip does not issue
another Write and Invalidate command on the next ownership unless the
address is aligned.