
PCI Cache Mode
3-9
3.3.6 Memory Read Multiple Command
This command is identical to the Memory Read command except that it
additionally indicates that the master may intend to fetch more than one
cache line before disconnecting. The SYM53C895 supports PCI Read
Multiple functionality and issues Memory Read Multiple commands on
the PCI bus when the Read Multiple Mode is enabled. This mode is
enabled by setting bit 2 of the DMODE register (ERMP). If cache mode
has been enabled, a Memory Read Multiple command is issued on all
read cycles, except op code fetches, when the following conditions have
been met:
1.
The CLSE and ERMP bits must be set.
2.
The Cache Line Size register must contain a legal burst size value
(2, 4, 8, 16, 32, 64, or 128) and that value must be less than or equal
to the DMODE burst size.
3.
The number of bytes to be transferred at the time a cache boundary
has been reached must be at least twice the full cache line size.
4.
The chip must be aligned to a cache line boundary.
When these conditions have been met, the chip issues a Memory Read
Multiple command instead of a Memory Read during all PCI read cycles.
3.3.6.1 Burst Size Selection
The Memory Read Multiple command reads in multiple cache lines of
data in a single bus ownership. The number of cache lines to be read is
a multiple of the cache line size as allowed in the
PCI Local Bus
Specication, Revision 2.1 standard. The logic selects the largest
multiple of the cache line size based on the amount of data to transfer,
with the maximum allowable burst size being determined from the
DMODE Burst Size bits and CTEST 5, bit 2.
3.3.6.2 Read Multiple with Read Line Enabled
When both the Read Multiple and Read Line modes have been enabled,
the Memory Read Line command is not issued if the above conditions
are met. Instead, a Memory Read Multiple command is issued, even
though the conditions for Read Line have been met.