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| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 18 of 84
DCLK
D[0:11]
CCDIN
CLI
SHD
(INTERNAL)
NN+1
N+2
N+15
N+14
N+13
N+12
N+8
N+7
N+6
N+5
N+4
N+3
N+16
N–14
N–4
N–5
N–6
N–7
N–8
N–9
N–10
N–11
N–12
N–13
N–3
N–2
N
N–1
SAMPLE PIXEL N
tCLIDLY
tDOUTINH
N–17
N–4
N–8
N–9
N–10
N–11
N–12
N–13
N–14
N–15
N–16
N–3
N–2
N
N–1
ADC DOUT
(INTERNAL)
N+11
N+10
N+9
N–7
N–6
N–5
N–17
N–15
N–16
N+17
NOTES
1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT WITH RESPECT TO CLI LOCATION.
3. INHIBIT TIME FOR DOUT PHASE IS DEFINED BY
tDOUTINH, WHICH IS EQUAL TO SHDLOC PLUS 11 EDGES. IT IS RECOMMENDED THAT
THE 12 EDGE LOCATIONS FOLLOWING SHDLOC NOT BE USED FOR THE DOUTPHASE LOCATION.
4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC.
5. RECOMMENDED VALUE FOR
tOD (DOUT DLY) IS 4ns.
6. THE DOUT LATCH CAN BE BYPASSED USING REGISTER 0x01, BIT [1] = 1 SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT
THE DATA OUTPUT PINS. THIS CONFIGURATION IS RECOMMENDED IF THE ADJUSTABLE DOUT PHASE IS NOT REQUIRED.
PIPELINE LATENCY = 16 CYCLES
05
58
6-
0
21
Figure 22. Digital Data Output Pipeline Delay
CLPOB and PBLK Masking Area
HORIZONTAL CLAMPING AND BLANKING
The AD9923A allows the CLPOB and/or PBLK signals to be
disabled during certain lines in the field without changing the
existing CLPOB and/or PBLK pattern settings.
The AD9923A horizontal clamping and blanking pulses are
fully programmable to suit a variety of applications. Individual
controls are provided for CLPOB, PBLK, and HBLK during
different regions of each field. This allows dark pixel clamping
and blanking patterns to be changed at each stage of the readout
to accommodate different image transfer timing and high speed
line shifts.
To use CLPOB masking, the CLPMASKSTART and CLPMASKEND
registers are programmed to specify the starting and ending lines
in the field where the CLPOB patterns are ignored. There are three
sets of CLPMASKSTART and CLPMASKEND registers,
allowing up to three CLPOB masking areas to be created.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 23. These two signals are independently
programmed using the registers in Table 12. SPOL is the start
polarity for the signal, and TOG1 and TOG2 are the first and
second toggle positions of the pulse. Both signals are active low
and should be programmed accordingly.
CLPOB masking registers are not specific to a given V-sequence;
they are active for any existing field of timing. To disable the
CLPOB masking feature, set these registers to the maximum
value, 0xFFF (default value).
To use PBLK masking, the PBLKMASKSTART and
PBLKMASKEND registers are programmed to specify the
starting and ending lines in the field where the PBLK patterns
are ignored. There are three sets of PBLKMASKSTART and
PBLKMASKEND registers, allowing the creation of up to three
PBLK masking areas.
A separate pattern for CLPOB and PBLK can be programmed
for each V-sequence. As described in the Vertical Timing
Generation section, several V-sequences can be created, each
containing a unique pulse pattern for CLPOB and PBLK.
Figure 46 shows how the sequence change positions divide the
readout field into regions. A different V-sequence can be
assigned to each region, allowing the CLPOB and PBLK signals
to change with each change in the vertical timing. Unused CLPOB
and PBLK toggle positions should be set to 8191.
PBLK masking registers are not specific to a given V-sequence;
they are active for any existing field of timing. To disable the
PBLK masking feature, set these registers to the maximum
value, 0xFFF (default value).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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