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| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 29 of 84
Generating Line Alternation for V-Sequences and HBLK
During low resolution readout, some CCDs require a different
number of vertical clocks on alternate lines. The AD9923A can
support such CCDs by using different VREP registers. This
allows a different number of VPAT repetitions to be programmed
on odd and even lines.
Note that only the number of repeats is different in odd and
even lines, but the VPAT group remains the same. There are
separate controls for the assigned Group A and Group B patterns.
Both Group A and Group B can support odd and even line
alternation. Group A uses the VREPA_1 and VREPA_2 regis-
ters; Group B uses the VREPB_ODD and VREPB_EVEN
registers. Group A can also support three-line and four-line
alternation by using the VREPA_3 and VREPA_4 registers.
Additionally, the HBLK signal can be alternated for odd and
even lines. When the HBLKALT = 1, the HBLKTOGE1 and
HBLKTOGE2 positions are used on odd lines, and the
HBLKTOGE3 to HBLKTOGE6 positions are used on even
lines. This allows the HBLK interval to be adjusted on odd
and even lines if needed.
Figure 41 shows an example of simultaneous VPAT repetition
alternation and HBLK alternation. Both types of alternation can
be used separately.
XV1
XV2
VREPA_1 = 2
(OR VREPB_ODD = 2)
VREPA_2 = 5
(OR VREPB_EVEN = 5)
VREPA_1 = 2
(OR VREPB_ODD = 2)
XV13
HD
NOTES
1. THE NUMBER OF REPEATS FOR V-PATTERN GROUP A OR GROUP B CAN BE ALTERNATED ON ODD AND EVEN LINES.
2. GROUP A ALSO SUPPORTS 3-LINE AND 4-LINE ALTERNATION USING THE ADDITIONAL VREPA_3 AND VREPA_4 REGISTERS.
3. THE HBLK TOGGLE POSITIONS CAN ALSO BE ALTERNATED BETWEEN ODD AND EVEN LINES TO GENERATE DIFFERENT HBLK PATTERNS
FOR ODD/EVEN LINES. SEE THE HORIZONTAL CLAMPING AND BLANKING SECTION FOR MORE INFORMATION ON HBLK.
HBLK
HBLKTOGE1
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE1
HBLKTOGE2
05
58
6-
04
0
Figure 41. Odd/Even Line Alternation of VPAT Repetitions and HBLK Toggle Positions
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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