- 您现在的位置：买卖IC网 > PDF目录11659 > AD9923ABBCZRL (Analog Devices Inc)IC PROCESSOR CCD 12BIT 105CSPBGA PDF资料下载
参数资料
| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 55/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页当前第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页
AD9923A
Rev. A | Page 59 of 84
H-COUNTER
RESET
VD
NOTES
1. INTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.
2. INTERNAL H-COUNTER IS ALWAYS RESET 32.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 33 OR 34 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 34 CLI RISING EDGES AFTER HD FALLING EDGE.
HD
CLI
XX
XX XX
X
H-COUNTER
(PIXEL COUNTER)
3ns MIN
XX
X
XXX
X
XX
X
XX
X
XX
X
3ns MIN
SHD
INTERNAL
HD
INTERNAL
tCLIDLY
X
32.5 CYCLES
012
X
XXX
X
XX
X
05
58
6-
07
5
Figure 77. External VD/HD and Internal H-Counter Synchronization, Slave Mode
05
58
6-
0
76
0123
4
H-COUNTER
RESET
VD
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 28 PIXELS OF PIXEL 0 LOCATION.
HD
H-COUNTER
(PIXEL
COUNTER)
N
N-1
N-2
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
N-3
N-4
N-5
N-6
N-7
N-8
N-9
N-10
N-11
N-12
N-13
N-14
N-15
N-16
N-17
N-18
N-19
N-20
N-21
N-22
N-23
N-24
N-25
N-26
N-27
N-28
Figure 78. Toggle Position Inhibited Area—Master Mode
H-COUNTER
RESET
05
58
6-
0
77
VD
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 28 PIXELS OF PIXEL 0 LOCATION.
HD
H-COUNTER
(PIXEL
COUNTER)
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
01
2
N-1
N
N-2
N-3
N-4
N-5
N-6
N-7
N-8
N-9
N-10
N-11
N-12
N-13
N-14
N-15
N-16
N-17
N-18
N-19
N-20
N-21
N-22
N-23
N-24
N-25
N-26
N-27
N-28
N-29
N-30
N-31
N-32
N-33
Figure 79. Toggle Position Inhibited Area—Slave Mode
Vertical Toggle Position Placement Near Counter Reset
One additional consideration during the reset of the internal
counters is the vertical toggle position placement. Prior to the
internal counters being reset, there is a region of 28 pixels
during which no toggle positions can be programmed.
As shown in Figure 78, in master mode, the last 28 pixels before
the HD falling edge should not be used for toggle position place-
ment of the XV, VSG, SUBCK, HBLK, PBLK, or CLPOB pulses.
Figure 79 shows the same example for slave mode. The same
restriction applies—the last 28 pixels before the counters are
reset cannot be used. However, the counter reset is delayed with
respect to VD/HD placement; therefore, the inhibited area is
different than it is in master mode.
It is also recommended that Pixel Location 0 is not used for
toggle positions for the VSG and SUBCK pulses.
相关PDF资料 |
PDF描述 |
|---|---|
| 1-413589-1 | CONN PLUG BNC JIS 3C-2V CRIMP AU |
| 8-5227079-1 | CONN PLUG BNC CRIMP DUAL |
| 2081204-1 | CONN JACK SMA BULKHEAD RG402 |
| MS3102R36-18S | CONN RCPT 31POS BOX MNT W/SCKT |
| AD8497CRMZ-R7 | IC THERMOCOUPLE A W/COMP 8MSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
发布紧急采购，3分钟左右您将得到回复。