- 您现在的位置：买卖IC网 > PDF目录11659 > AD9923ABBCZRL (Analog Devices Inc)IC PROCESSOR CCD 12BIT 105CSPBGA PDF资料下载
参数资料
| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 54/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页当前第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页
AD9923A
Rev. A | Page 58 of 84
VD
HD
SUSPEND
SYNC
HL, H1 TO H4, RG,
XV1 TO XV13,
VSG1 TO VSG8, SUBCK
NOTES
1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x14).
4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.
5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
05
58
6-
07
4
Figure 76. SYNC Timing to Synchronize AD9923A with External Timing
Generating Software Sync Without External Sync Signal
If an external sync pulse is not available, it is possible to generate
an internal sync pulse by writing to the SYNCPOL register
(Address 0x13). If the software SYNC option is used, the SYNC
input (Pin 35) should be low (VSS) during the power-up proce-
dure. After the power-up procedure is complete, the SYNC pin
can be used as an output by setting the SYNCENABLE register
low (Address 0x12).
After power-up, follow Step 1 to Step 9 of the procedure in the
For Step 10, instead of using the external sync pulse, write 1 to
the SYNCPOL register to generate an internal sync pulse and
begin the timing operation.
SYNC During Master Mode Operation
The SYNC input can be used anytime during master mode
operation to synchronize the AD9923A counters with external
timing, as shown in Figure 76.
To suspend operation of the digital outputs during the SYNC
operation, set the SYNCSUSPEND register (Address 0x14) to 1. If
SYNCSUSPEND = 1, the polarities of the outputs are held at the
same state as when OUTCONTROL = low, as shown in Table 43
and Table 44.
Power-Up and Synchronization in Slave Mode
The power-up procedure for slave mode operation is the same
as the procedure described for master mode operation, with
two exceptions:
Eliminate Step 8. Do not configure the part for master
mode timing.
No sync pulse is required in slave mode. Substitute Step 10
with starting the external VD and HD signals. This
synchronizes the part, allows the register updates, and
starts the timing operation.
Note that DCLK does not begin to transition until Step 7 is
complete.
When the AD9923A is in slave mode, the VD/HD inputs
synchronize the internal counters. After a falling edge of VD,
there is a latency of 34 master clock edges (CLI) after the falling
edge of HD until the internal H-counter is reset. The reset
operation is shown in Figure 77.
Note that if SHDLOC is set so that the 3 ns minimum delay
between the rising edge of SLI and the falling edge of the
internal SHD signal is not met, the internal H-counter can reset
after only 33 master clock edges (CLI).
相关PDF资料 |
PDF描述 |
|---|---|
| 1-413589-1 | CONN PLUG BNC JIS 3C-2V CRIMP AU |
| 8-5227079-1 | CONN PLUG BNC CRIMP DUAL |
| 2081204-1 | CONN JACK SMA BULKHEAD RG402 |
| MS3102R36-18S | CONN RCPT 31POS BOX MNT W/SCKT |
| AD8497CRMZ-R7 | IC THERMOCOUPLE A W/COMP 8MSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
发布紧急采购，3分钟左右您将得到回复。