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| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 26 of 84
Vertical Sequences (VSEQ)
A vertical sequence (VSEQ) is created by selecting one of the
V-pattern groups and adding repeats, a start position, and
horizontal clamping and blanking information. Each VSEQ is
shows how each register is used to generate a V-sequence.
The VPATSELA and VPATSELB registers select the V-pattern
group that is used in a given V-sequence. Having two groups
available allows each vertical output to be mapped to a different
V-pattern group. The selected V-pattern group can have
repetitions added for high speed line shifts or line binning by
using the VREP registers for odd and even lines. Generally, the
same number of repetitions is programmed into both registers.
If a different number of repetitions is required on odd and even
lines, separate values can be used for each register (see the
section). The VSTARTA and VSTARTB registers specify the pixel
location where the V-pattern group starts. The VMASK register is
used in conjunction with the FREEZE/RESUME registers to enable
optional masking of the XV outputs. Either or both of the
FREEZE1/RESUME1 and FREEZE2/RESUME2 registers can be
enabled.
The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 8192. Note that the last line of the
field can be programmed separately using the HDLAST register,
located in the field register (see Table 17).
VREP 3
HD
XV1 TO XV13
PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE:
1START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP.
2HD LINE LENGTH.
3V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP.
4NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED).
5START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS.
6MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL.
V-PATTERN GROUP
1
3
CLPOB
PBLK
HBLK
2
44
VREP 2
5
6
05
58
6-
03
6
Figure 37. V-Sequence Programmability
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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