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| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 25 of 84
Vertical Pattern (VPAT) Groups
A vertical pattern (VPAT) group defines the individual pulse
pattern for each XV1 to XV13 output signal. Table 15 summarizes
the registers that are available for generating each VPAT group.
The first, second, third, fourth, fifth, and sixth toggle positions
(XVTOG1, XVTOG2, XVTOG3, XVTOG4, XVTOG5,
XVTOG6) are the pixel locations where the pulse transitions. All
toggle positions are 13-bit values that can be placed anywhere in
the horizontal line.
More registers are included in the vertical sequence registers to
specify the output pulses: XV1POL to XV13POL specifies the
start polarity for each signal, VSTART specifies the start
position of the VPAT group, and VLEN designates the total
length of the VPAT group, which determines the number of
pixels between each pattern repetition, if repetitions are used.
To achieve the best possible noise performance, ensure that
VSTART + VLEN < the end of the H-blank region.
Toggle positions programmed to either Pixel 0 or Pixel 8191 are
ignored. The toggle positions of unused XV-channels must be
programmed to either Pixel 0 or Pixel 8191. This prevents unpre-
dictable behavior because the default values of the V-pattern
group registers are unknown.
Table 15. Vertical Pattern Group Registers
Register
Length (Bits)
Range
Description
XVTOG1
13
0 to 8191 pixel location
First toggle position within line for each XV1 to XV12 output
XVTOG2
13
0 to 8191 pixel location
Second toggle position
XVTOG3
13
0 to 8191 pixel location
Third toggle position
XVTOG4
13
0 to 8191 pixel location
Fourth toggle position
XVTOG5
13
0 to 8191 pixel location
Fifth toggle position
XVTOG6
13
0 to 8191 pixel location
Sixth toggle position
HD
XV1
PROGRAMMABLE SETTINGS:
1START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION (A TOTAL OF SIX TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).
4TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS).
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.
4
1
2
3
XV2
1
23
XV12
1
2
3
05
58
6-
03
5
Figure 36. Vertical Pattern Group Programmability
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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