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| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 59/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 62 of 84
CIRCUIT LAYOUT INFORMATION
The AD9923A typical circuit connections are shown in Figure 82.
The PCB layout is critical for achieving good image quality from
the AD9923A. All supply pins, particularly the pins for the AVDD,
TCVDD, RGVDD, and HVDD supplies, must be decoupled to
ground with quality, high frequency chip capacitors.
The decoupling capacitors should be as close as possible to the
supply pins and have a very low impedance path to a continuous
ground plane. There should be a bypass capacitor of at least
4.7 μF for each main supply—AVDD, HVDD, and DRVDD—
but this is not necessary for each individual pin. In most
applications, it is easier to share the supply for RGVDD and
HVDD; this requires bypassing each supply pin separately. A
separate 3 V supply can also be used for DRVDD, but it should
be decoupled to the same ground plane as the rest of the chip. A
separate ground for DRVSS is not recommended.
The analog bypass pins (REFT and REFB) should be carefully
decoupled to ground, as close as possible to their respective
pins. The analog input (CCDIN) capacitor should also be
located close to the pin.
To avoid excessive distortion of the signals, design the HL, H1
to H4, and RG traces to have low inductance. To minimize
mutual inductance, route the complementary signals, H1 and
H2, as symmetrically and close together as possible. The same
should be done for the H3 and H4 signals. Heavier PCB traces
are recommended because of the large transient current
demand placed by the CCD on HL and H1 to H4. If possible,
physically locating the AD9923A closer to the CCD reduces the
inductance on these lines. The routing path should be as direct
as possible from the AD9923A to the CCD.
The AD9923A also contains an on-chip oscillator for driving an
external crystal. The maximum crystal frequency that the
AD9923A can support is 36 MHz. Figure 80 shows an example
application using a typical 24 MHz crystal. For the exact values
of the external resistors and capacitors, see the crystal
manufacturer’s data sheet.
10pF~20pF
CLI (H12)
CLO (J12)
AD9923A
24MHz
XTAL
~2M
~375
05
58
6-
0
78
Figure 80. Crystal Driver Application
0V
VDD
VL
V5V
VH
VDR_EN
05
58
6-0
8
0
Figure 81. AD9923A Recommended Power up Sequence
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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