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| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 43/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 48 of 84
Table 39. SUBCK and TRIGGER Register Parameters
Register
Length
(Bits)
Range
Description
TRIGGER
8
On/off for eight signals
0: triggers SHUT0 signal.
1: triggers SHUT1 signal.
2: triggers SHUT2 signal.
3: triggers SHUT3 signal.
4: triggers VSUB0 signal.
5: triggers VSUB1 signal.
6: triggers EXPOSURE operation.
7: triggers READOUT operation.
READOUTNUM
3
0 to 7 fields
Number of fields to suppress SUBCK after exposure.
EXPOSURENUM
12
0 to 4095 fields
Number of fields to suppress to SUBCK and VSG during exposure time (low
speed shutter).
VDHDOFF
1
On/off
Disable VD/HD output during exposure.
1 = disable VD.
0 = enable VD.
SUBCKPOL1
1
High/low
SUBCK start polarity for SUBCK1 and SUBCK2.
SUBCK1TOG11
12
0 to 4095 pixel locations
First toggle positions for first SUBCK pulse (normal shutter).
SUBCK1TOG21
12
0 to 4095 pixel locations
Second toggle positions for first SUBCK pulse (normal shutter).
SUBCK2TOG11
12
0 to 4095 pixel locations
First toggle positions for second SUBCK pulse in last line (high precision).
SUBCK2TOG21
12
0 to 4095 pixel locations
Second toggle positions for second SUBCK pulse in last line (high precision).
12
1 to 4095 pulses
Total number of SUBCKs per field, at one pulse per line.
12
0 to 4095 pulses
Number of pulses, after the VSG line, to suppress SUBCK.
SUBCKMASK1
2
0 to 3 masking mode
Additional masking of SUBCK output.
0 = no additional mask.
1 = start mask at VD edge.
2 = use internal SHUT3 signal to mask.
1 Register is not VD updated but updated at the start of the line after the sensor gate line.
Shutter Outputs
The AD9923A contains three shutter output pins: VSUB,
MSHUT, and STROBE. Internally, there are six possible shutter
signals available: VSUB0, VSUB1, SHUT0, SHUT1, SHUT2,
and SHUT3. Any of these signals, and the following combinations:
SHUT0 ^ VSUB0, SHUT0 ^ VSUB1, SHUT0 ^ SHUT1,
SHUT0 ^ SHUT2, can be mapped to any of the output pins
using the VSUB_CTRL, MSHUT_CTRL, and STROBE_CTRL
registers.
The VSUB signals behave differently than the SHUT signals,
and are generally used for the VSUB output pin. If a more generic
approach is desired for the shutter signals, the SHUT signals can
be used for the VSUB output pin.
It is also possible to configure the SYNC pin as an output and
send one of the internal shutter signals, or the combinations listed
above, to the SYNC pin using the TESTO_CTRL register
function. This provides the flexibility of outputting up to four
shutter outputs if the external SYNC input function is not needed.
VSUB Signal Operation
The CCD readout bias (VSUB) can be programmed to accom-
modate different CCDs. Figure 67 shows two available modes.
In Mode 0, VSUB goes active when the exposure begins during
the field of the last SUBCK. The on position (rising edge in
Figure 67) is programmable to any line within the field. VSUB
remains active until the end of the image readout. In Mode 1,
the VSUB is not activated until the start of the readout.
A function called VSUB_KEEPON is also available. When the
appropriate VSUB_KEEPON bit is set high, the VSUB output
remains active, even after the readout has finished. To disable
the VSUB at a later time, return this bit to low.
The AD9923A contains two programmable VSUB signals,
VSUB0 and VSUB1. Either of these signals can be mapped to
the VSUB output pin, the MSHUT pin, or the STROBE pin.
SHUT Signal Operation
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| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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