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| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 23 of 84
Increasing H-Clock Width During HBLK
The AD9923A allows the H1 to H4 pulse width to be increased
during the HBLK interval. The H-clock pulse width can in-
crease by reducing the H-clock frequency (see Table 14).
The HBLKWIDTH register (Register 0x35, Bits[6:4]) is a 3-bit
register that allows the H-clock frequency to be reduced by 1/2,
1/4, 1/6, 1/8, 1/10, 1/12, or 1/14. The reduced frequency only
occurs for H1 to H4 pulses that are located within the HBLK area.
Horizontal Timing Sequence Example
Figure 33 shows an example of a CCD layout. The horizontal
register contains 28 dummy pixels that occur on each line
clocked from the CCD. In the vertical direction, there are 10
optical black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 OB pixels in the back.
Figure 34 shows the basic sequence layout to use during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for CLPOB signals. PBLK is optional and it is often
used to blank the digital outputs during the noneffective CCD
pixels. HBLK is used during the vertical shift interval.
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers. More elaborate clamping schemes can
be used, such as adding a separate sequence to clamp during the
entire line of OB pixels. This requires configuring a separate
V-sequence for reading the OB lines.
The CLPMASKSTART and CLPMASKEND registers can be used
to disable the CLPOB on a few lines without affecting the setup of
the clamp sequences.
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL
OB LINES
2 VERTICAL
OB LINES
V
H
05
58
6-
03
2
Figure 33. CCD Configuration Example
Table 14. HBLK Width Register
Register
Length (Bits)
Range
Description
HBLKWIDTH
3
1× to 1/14× pixel rate
Controls H1 to H4 width during HBLK as a fraction of pixel rate
0: same frequency as the pixel rate
1: 1/2 pixel frequency, that is, doubles the H1 to H4 pulse width
2: 1/4 pixel frequency
3: 1/6 pixel frequency
4: 1/8 pixel frequency
5: 1/10 pixel frequency
6: 1/12 pixel frequency
7: 1/14 pixel frequency
VERTICAL SHIFT
VERT. SHIFT
CCDIN
SHP
SHD
HL/H1/H3
H2/H4
HBLK
PBLK
CLPOB
OPTICAL BLACK
DUMMY
EFFECTIVE PIXELS
OPTICAL BLACK
HD
0
55
86
-03
3
Figure 34. Horizontal Sequence Example
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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