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| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 27 of 84
Table 16. V-Sequence Registers1
Register
Length
(Bits)
Range
Description
HOLD
1
On/off
Use in conjunction with VMASK. 1 = hold instead of FREEZE/RESUME.
VMASK
2
0 to 3 mask mode
Enables the masking of XV1 to XV13 outputs at the locations specified by
the FREEZE/RESUME registers.
0 = no mask.
1 = enable FREEZE1/RESUME1.
2 = enable FREEZE2/RESUME2.
3 = enable both FREEZE1/RESUME1 and FREEZE2/RESUME2.
HDLEN
13
0 to 8191 pixels
HD line length in each V-sequence.
XV1POL to
XV13POL
1
High/low
Start polarity for each XV1 to XV13 output.
GROUPSEL
12
1b for each XV output
Assigns each XV1 to XV13 output to either V-Pattern Group A or
V-Pattern Group B.
0 = assigns to VPATSELA.
1 = assigns to VPATSELB.
TWO_GROUP
1
High/low
When high, all XV outputs combine Group A and Group B.
VPATSELA
5
0 to 31 V-pattern number
Selected V-pattern for Group A.
VPATSELB
5
0 to 31 V-pattern number
Selected V-pattern for Group B. If SPVTP_ENABLE = 1, VPATSELB is used
for second VTP inserted in SPVTP_ACTLINE.
VPATA_MODE
2
0 to 3 repetition mode
Selects alternation repetition mode for Group A only.
0 = disable alternation, use VREPA_1 for all lines.
1 = 2-line. Alternate VREPA_1 and VREPA_2 (same as odd/even).
2 = 3-line. Alternate VREPA_1, VREPA_2, and VREPA_3.
3 = 4-line. Alternate VREPA_1, VREPA_2, VREPA_3, and VREPA_4.
VSTARTA
13
0 to 8191 pixel location
Start position for the selected V-Pattern Group A.
VSTARTB
13
0 to 8191 pixel location
Start position for the selected V-Pattern Group B. If SPVTP_ENABLE = 1,
VSTARTB is used for start position of VPATSELB in SPVTP_ACTLINE.
VLENA
13
0 to 8191 pixels
Length of selected V-Pattern Group A.
VLENB
13
0 to 8191 pixels
Length of selected V-Pattern Group B.
VREPB_ODD
12
0 to 4095 repeats
Number of repetitions for the V-Pattern Group B for odd lines.
If no alternation is required for Group B, set VREPB_ODD equal to
VREPB_EVEN.
VREPB_EVEN
12
0 to 4095 repeats
Number of repetitions for the V-Pattern Group B for even lines.
If no alternation is required for Group B, set VREPB_EVEN equal to
VREPB_ODD.
VREPA_1
12
0 to 4095 repeats
Number of repetitions for the V-Pattern Group A for first lines (odd).
VREPA_2
12
0 to 4095 repeats
Number of repetitions for the V-Pattern Group A for second lines (even).
VREPA_3
12
0 to 4095 repeats
Number of repetitions for the V-Pattern Group A for third lines.
VREPA_4
12
0 to 4095 repeats
Number of repetitions for the V-Pattern Group A for fourth lines.
FREEZE1
13
0 to 8191 pixel location
Pixel location where the XV outputs freeze or hold (see VMASK).
RESUME1
13
0 to 8191 pixel location
Pixel location where the XV outputs resume operation (see VMASK).
FREEZE2
13
0 to 8191 pixel location
Pixel location where the XV outputs freeze or hold (see VMASK).
RESUME2
13
0 to 8191 pixel location
Pixel location where the XV outputs resume operation (see VMASK).
SPVTP_ACTLINE
12
0 to 4095 line location
Active line for second VTP insertion.
SPVTP_ENABLE
1
High/low
When high, second VTP is inserted into SPVTP_ACTLINE.
1 See Table 12 and Table 13 for CLPOB, PBLK, and HBLK registers.
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相关代理商/技术参数 |
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|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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