参数资料
型号: AD9923ABBCZRL
厂商: Analog Devices Inc
文件页数: 53/84页
文件大小: 0K
描述: IC PROCESSOR CCD 12BIT 105CSPBGA
标准包装: 2,000
类型: CCD 信号处理器,12 位
输入类型: 逻辑
输出类型: 逻辑
接口: 3 线串口
电流 - 电源: 20mA
安装类型: 表面贴装
封装/外壳: 105-LFBGA,CSPBGA
供应商设备封装: 105-CSPBGA(8x8)
包装: 带卷 (TR)
AD9923A
Rev. A | Page 57 of 84
10.
Generate a SYNC event. If SYNC is high at power-up,
bring SYNC input low for a minimum of 100 ns. Then,
bring SYNC high. This causes the internal counters to
reset and starts a VD/HD operation. The first VD/HD
edge allows VD register updates to occur, including
OUTCONTROL to enable all outputs. If an external
SYNC pulse is not available, generate an internal SYNC
pulse by writing to the SYNCPOL register as described in
Signal section.
POWER
SUPPLIES
SERIAL
WRITES
VD
(OUTPUT)
1H
FIRST FIELD
SYNC
(INPUT)
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUTCONTROL
REGISTER IS UPDATED AT VD/HD EDGE.
H1/H3, RG, DCLK, STROBE, MSHUT, VSUB
CLI
(INPUT)
HD
(OUTPUT)
tSYNC
0V
VH SUPPLY
VL SUPPLY
(HI-Z BY DEFAULT)
2
34
5
6
779
10
1V
5
1
+3V SUPPLIES
VDR_EN
8
(AND INTERNAL XV1 TO XV13, VSG1 TO VSG8, XSBUCK, XSUBCNT)
0V
+3V
VH
VM
VL
V1 TO V13
VM
05
58
6-
0
73
Figure 75. Recommended Power-Up Sequence and Synchronization, Master Mode
Table 42. Power-Up Register Write Sequence
Register
Address
Data
Description
SW_RST
0x10
0x01
Resets all registers to default values
0x20 to 0xFFF
User defined
Horizontal, vertical, shutter timing
STANDBY
0x00
0x04
Powers up the AFE
TEST3
0xEA
0x60
Set TEST3 register to required value
OSC_RST
0x16
0x01
Resets crystal oscillator circuit
TGCORE_RSTB
0x15
0x01
Resets internal timing core
MASTER
0x20
0x01
Configures master mode
OUTCONTROL
0x11
0x01
Enables all outputs after SYNC
SYNCPOL
0x13
0x01
SYNC active polarity (for software SYNC only)
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