参数资料
型号: AD9923ABBCZRL
厂商: Analog Devices Inc
文件页数: 25/84页
文件大小: 0K
描述: IC PROCESSOR CCD 12BIT 105CSPBGA
标准包装: 2,000
类型: CCD 信号处理器,12 位
输入类型: 逻辑
输出类型: 逻辑
接口: 3 线串口
电流 - 电源: 20mA
安装类型: 表面贴装
封装/外壳: 105-LFBGA,CSPBGA
供应商设备封装: 105-CSPBGA(8x8)
包装: 带卷 (TR)
AD9923A
Rev. A | Page 31 of 84
Hold Area Using FREEZE/RESUME Registers
The FREEZE/RESUME registers can also be used to create a
hold area, in which the XV outputs are temporarily held and
then later resume at the point where they were held. As shown
in Figure 44, this is different than using the VMASK register,
because the XV outputs continue from where they stopped (as
opposed to having the pixel counter run continuously), with
any toggle positions that fall between the FREEZE and
RESUME locations being ignored. Signals assigned to Group B
are not affected by the hold area.
XV1
XV11
HD
NOTES
1. WHEN HOLD = 1 FOR ANY V-SEQUENCE, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA FOR GROUP A.
2. ABOVE EXAMPLE: ALL XV-OUTPUTS ARE ASSIGNED TO GROUP A.
3. H-COUNTER FOR GROUP A (XV1 TO XV13) STOPS DURING HOLD AREA.
XV12
HOLD AREA
FOR GROUP A
XV13
FREEZE
RESUME
05
58
6-
0
43
Figure 44. Hold Area for Group A
XV1
XV11
HD
NOTES
1. ABOVE EXAMPLES: XV12 AND XV13 ARE ASSIGNED TO GROUP B.
2. GROUP B DOES NOT USE HOLD AREA.
XV12
HOLD AREA
FOR GROUP A
XV13
NO HOLD
AREA FOR
GROUP B
FREEZE
RESUME
05
58
6-
04
4
Figure 45. Group B Does Not Use Hold Area
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