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| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 32 of 84
Complete Field: Combining V-Sequences
After the V-sequences are created, they are combined to create
different readout fields. A field consists of up to nine regions.
Within each region, a different V-sequence can be selected.
Figure 46 shows how the sequence change position (SCP)
registers designate the line boundary for each region and how
the VSEQSEL registers select the V-sequence for each region.
Registers to control the VSG outputs are also included in the
field registers. Table 17 summarizes the registers used to create
the different fields.
The VSEQSEL registers, one for each region, select which
V-sequences are active during each region. The SWEEP
registers can enable the sweep mode during any region.
The MULTI registers are used to enable the multiplier mode
during any region. The SCP registers create the line boundaries
for each region. The VDLEN register specifies the total number
of lines in the field. The total number of pixels per line (HDLEN)
is specified in the V-sequence registers, and the HDLAST
register specifies the number of pixels in the last line of the
field. HDLEN, VDLEN, HDLAST registers are ignored when
the part is in slave mode. The VPATSECOND register is used to
add a second V-pattern group to the XV1 to X12 outputs during
the sensor gate (VSG) line.
The SGMASK register is used to enable or disable each VSG
output. There are two bits for each VSG output to enable
separate masking during SGACTLINE1 and SGACTLINE2.
Setting a masking bit high disables, or masks, the output; setting it
low enables the output. The SGPATSEL register assigns one of the
eight SG patterns to each VSG output. Each SG pattern is created
separately using the SG pattern registers. The SGACTLINE1
register specifies which line in the field contains the VSG
outputs. The optional SGACTLINE2 register allows the same
VSG pulses to repeat on a different line, although separate
masking is available for SGACTLINE1 and SGACTLINE2.
Table 17. Field Registers
Register
Length
(Bits)
Range
Description
VSEQSEL
5
0 to 31 V-sequence
number
Selected V-sequence for each region in the field.
SWEEP
1
High/low
Enables sweep mode for each region when set high.
MULTI
1
High/low
Enables multiplier mode for each region when set high.
SCP
12
0 to 4095 line number
Sequence change position (SCP) for each region.
VDLEN
12
0 to 4095 lines
Total number of lines in each field.
HDLAST
13
0 to 8191 pixels
Length in pixels of the last HD line in each field.
VSTARTSECOND
13
0 to 8191 pixels
Start position of the second V-pattern group applied during VSG line.
VPATSECOND
5
0 to 31 V-pattern
group number
Selected V-pattern group for the second pattern applied during VSG line.
SGMASK
16
High/low, each VSG
Set high to mask each VSG output. Two bits for each VSG output: one for SGLINE1,
and one for SGLINE2.
[0] Masking for VSG1 on SGLINE1.
[1] Masking for VSG1 on SGLINE2.
[2] Masking for VSG2 on SGLINE1.
[3] Masking for VSG2 on SGLINE2.
[15] Masking for VSG8 on SGLINE1.
[16] Masking for VSG8 on SGLINE2.
SGPATSEL
24
0 to 7 pattern
number, each VSG
Selects the VSG pattern number for each VSG output. VSG1[2:0], VSG2[5:3],
VSG3[8:6], VSG4[11:9], VSG5[14:12], VSG6[17:15], VSG7[20:18], VSG8[23:21].
SGACTLINE1
12
0 to 4095 line number
Selects the line in the field where the VSG is active.
SGACTLINE2
12
0 to 4095 line number
Selects a second line in the field to repeat the VSG signals.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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