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参数资料
| 型号： | AD9923ABBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/84页 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 20mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 105-LFBGA，CSPBGA |
| 供应商设备封装： | 105-CSPBGA（8x8） |
| 包装： | 带卷 (TR) |
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AD9923A
Rev. A | Page 24 of 84
VERTICAL TIMING GENERATION
The AD9923A provides a very flexible solution for generating
vertical CCD timing; it can support multiple CCDs and different
system architectures. The 13-phase vertical transfer clocks, XV1 to
XV13, are used to shift lines of pixels into the horizontal output
register of the CCD. The AD9923A allows these outputs to be
individually programmed into various readout configurations,
using a four-step process as shown in Figure 35.
1.
Use the vertical pattern group registers to create the individual
pulse patterns for XV1 to XV13.
2.
Use the V-pattern groups to build the sequences and add more
information.
3.
Construct the readout for an entire field by dividing the field
into regions and assigning a sequence to each region. Each
field can contain up to nine regions to accommodate different
steps, such as high speed line shifts and unique vertical line
transfers, of the readout. The total number of V-patterns,
V-sequences, and fields are programmable and limited by the
number of registers. High speed line shifts and unique vertical
transfers are examples of the different steps required for
readout.
4.
Use the MODE register to combine fields in any order for
various readout configurations.
CREATE THE VERTICAL PATTERN GROUPS,
UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.
XV1
XV2
XV11
XV12
XV1
XV2
XV3
XV11
XV12
VPAT 0
VPAT 1
1
USE THE MODE REGISTER TO CONTROL WHICH FIELDS
ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN
FIELDS MAY BE COMBINED IN ANY ORDER).
FIELD 3
FIELD 4
FIELD 0
FIELD 1
FIELD 2
FIELD 5
FIELD 1
FIELD 4
FIELD 2
4
BUILD THE V-SEQUENCES BY ADDING START POLARITY,
LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,
GROUP A/B INFORMATION, AND HBLK/CLPOB PULSES.
V-SEQUENCE 0
(VPAT0, 1 REP)
V-SEQUENCE 1
(VPAT1, 2 REP)
V-SEQUENCE 2
(VPAT1, N REP)
XV1
XV2
XV11
XV12
XV3
XV1
XV2
XV11
XV12
XV3
XV1
XV2
XV11
XV12
XV3
2
FIELD 0
FIELD 1
FIELD 2
REGION 0: USE V-SEQUENCE 2
REGION 1: USE V-SEQUENCE 0
REGION 3: USE V-SEQUENCE 0
REGION 4: USE V-SEQUENCE 2
REGION 2: USE V-SEQUENCE 3
3 BUILD EACH FIELD BY DIVIDING IT INTO DIFFERENT
REGIONS AND ASSIGNING A V-SEQUENCE TO EACH
(MAXIMUM OF NINE REGIONS IN EACH FIELD).
05
58
6-
0
34
Figure 35. Summary of Vertical Timing Generation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9923BBCZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9923BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9924BBCZ | 制造商:Analog Devices 功能描述: |
| AD9924BBCZRL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9925 | 制造商:AD 制造商全称:Analog Devices 功能描述:CCD Signal Processor with Vertical Driver and Precision Timing Generator |
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