参数资料
| 型号： | IP-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 102/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 初始许可证 |
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D–2
Adjust the PLL Phases
Adjust the PLL Phases
There is no automatic setup of the fedback PLL, or the resyncronization and
postamble clock phases in fedback clock DQS mode (refer to Figure A–2 on page A–6 ).
To adjust the PLL phases, follow these steps:
1. On the Manual Timing tab, turn on Manual resynchronization control and
Manual postamble control .
2. In Postamble clock setting , choose Dedicated clock .
3. Click Show Timing Estimates .
1
The following parameters must be set in the given order.
4. Balance the following setup and hold time properties on the Show Timing
Estimates window, by adjusting the relevant parameter on the Manual Timing
tab.
a. For Stage 1 Resynchronization , adjust the resynchronization fedback clock
phase.
b. For Stage 2 Resynchronization , adjust the resynchronize captured read data in
cycle.
c. For Stage 1 Postamble Control , adjust the postamble dedicated clock phase.
d. For Stage 1 Postamble Control , adjust the postamble cycle.
You can now set up constraints and generate your custom variation.
Assign Pins
When you compile a project, the add_constraints_for_ < variation name > .tcl script
automatically assigns the DQ/DQS pins. To assign the other pins that are needed for
the DDR2 SDRAM interface on the Stratix II Memory Board 2, run the
< install directory > /lib/stratix_s2mb2_pins.tcl .
Place the Fedback PLL
The fedback PLL needs to be driven directly from the input pin, and not routed
through the FPGA, otherwise the Quartus II software issues a warning and your
design does not meet timing.
On the Stratix II Memory Board 2 the fedback clock input pin is on the side of the
device, and the memory interface is on the top. Because the example design feeds the
DLL from the fedback PLL by default, the PLL is automatically placed on the top and
its clock input is therefore routed through the FPGA. To improve the design’s
timing, you should manually place the PLL on the side and drive the DLL input from
the system clock. If the fedback clock input pin is on the same side as the DQ pins, the
DLL may be fed from the fedback PLL.
? March 2009 Altera Corporation
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