参数资料
型号: IP-SDRAM/DDR2
厂商: Altera
文件页数: 53/106页
文件大小: 0K
描述: IP DDR2 SDRAM CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: DDR2 SDRAM 控制器
许可证: 初始许可证
Chapter 3: Functional Description
Device-Level Description
Figure 3–12 shows the testbench and the example design.
3–17
1
Ensure that the example driver is not optimized away in your example design, by
preserving the pnf output. Either attach it to a pin or assign it as a virtual pin in your
Quartus II project.
Figure 3–12. Testbench & Example Design
Testbench
Example Design
pnf
test_complete
clock_source
Example Dri v er
PLL
DDR SDRAM Controller
DLL
DDR SDRAM
DIMM Model
Bidrectional Board
Delay Model
Table 3–5 describes the files that are associated with the example design and the
testbench.
Table 3–5. Example Design & Testbench Files
Filename
<project name> _tb.v or .vhd (1)
<project name> .v or .vhd (1)
ddr_pll_ <device family> .v or .vhd (2)
ddr_fb_pll_stratixii.v or .vhd
<variation name> _example_driver.v or .vhd
<variation name> .v or .vhd
Description
Testbench for the example design.
Example design.
Example PLL.
Optional fed-back PLL (Stratix II devices only).
Example driver.
Top-level description of the custom MegaCore function.
Notes to Table 3–5 :
(1) <project name> is the name of the IP Toolbench-generated example design.
(2) Replace <device family> with stratix for Stratix series, or cyclone for Cyclone series.
The example driver is a self-checking test generator for the DDR or DDR2 SDRAM
controller. It uses a state machine to write data patterns to a range of column
addresses, within a range of row addresses in all memory banks. It then reads back
the data from the same locations, and checks that the data matches. The pass not fail
( pnf ) output transitions low if any read data fails the comparison. There is also a
pnf_per_byte output, which shows the comparison on a per byte basis. The
test_complete output transitions high for a clock cycle at the end of the write or
read sequence. After this transition the test restarts from the beginning.
The data patterns used are generated using an 8-bit LFSR per byte, with each LFSR
having a different initialization seed.
? March 2009
Altera Corporation
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