参数资料
| 型号： | IP-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 33/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 初始许可证 |
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Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
4. Click Next .
5. Edit the PLL parameters in the ALTPLL MegaWizard Plug-In.
2–23
f
For more information on the ALTPLL megafunction, refer to the Quartus II Help or
click Documentation in the ALTPLL MegaWizard Plug-In.
Compile & Perform Timing Analysis
When you compile a project after generating or editing and re-generating your
variation, the auto_add_ddr_constraints.tcl script automatically calls the constraints
script specific to each instance of the controller in your design. Each constraints script
performs the following procedure:
■
■
■
Checks if there is a remove_constraints.tcl script specific to this instance of the
controller, and if so, runs it to remove the previous set of constraints.
Analyses and elaborates the design to detect the exact hiearchy and then adds the
new set of constraints.
Creates a new, matching remove_constraints.tcl script, which you can use to
remove the constraints from your design, if necessary.
1
1
If the script successfully adds the new constraints, it does not run when you next
compile.
To prevent the constraints script from running, turn off Automatically run add
constraints script in the wizard. To manually prevent the script from running, open a
Quartus II Tcl Console window and enter the following command:
set_global_assignment -name PRE_FLOW_SCRIPT_FILE -remove
The constraints script analyzes and elaborates your design, to automatically extract
the hierarchy to your variation. To prevent the constraints script analyzing and
elaborating your design, turn on Enable Hierarchy Control in the wizard, and enter
the correct hierarchy path to your datapath (refer to step 24 on page 2–13 ).
To compile your design, choose Start Compilation (Processing menu), which runs the
add constraints scripts, compiles the example design, and performs timing analysis.
If the compilation does not reach the frequency requirements, follow these steps:
1. Choose Settings (Assignments menu).
2. Click Analysis & Synthesis Settings in the Category list.
3. In Optimization Technique , select Speed .
4. Click Fitter Settings in the Category list.
5. In Fitter effort , select Standard Fit (highest effort) .
6. Click OK .
7. Recompile the example design by clicking Start Compilation (Processing menu).
1
To achieve a higher frequency, turn on the Insert extra pipeline registers in
the datapath option (refer to step 5 on page 2–12 ).
? March 2009
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
| IP-VITERBI/SS | IP VITERBI LOW-SPEED |
| IP4220CZ6,125 | IC USB DUAL ESD PROTECT 6TSOP |
| IPA-66-1-600-10.0-A-01-T | CIRC BRKR 10A 2POLE SCREW TERM |
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参数描述 |
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| IPSE.4.62SM600 | 制造商:Banner Engineering 功能描述:FIBER IPSE.4.62SM600 GLASS FIBER (MIN ORDER 50) |
| IPS-EMBEDDED | 功能描述:开发软件 Embedded IP Suite MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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