参数资料
| 型号： | IP-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 74/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 初始许可证 |
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3–38
Chapter 3: Functional Description
Parameters
For minimum timing requirements, the values in the actual column must be greater
than or equal to the requirement; for maximum timing requirements, the figure in the
actual column must be less than or equal to the requirement. You can choose whether
to set the values in the cycle column or allow the wizard to choose the most
appropriate values.
Table 3–18 shows the memory timing parameters.
Table 3–18. Memory Timing Parameters
Parameter
Manually choose
clock cycles
t REFI
t INIT
t RP
t RCD
t RFC
t WR
t RAS
t MRD
t WTR
Range
On or Off
≤ 65534
≤ 65534
2 to 5
2 to 5
7 to 31
2 to 5
4 to 15
2 to 3
1 to 3
Description
Turn on, to enter values in the cycles column; turn off and the wizard calculates the
values in the cycles column.
Interval between refresh commands (maximum). The controller performs regular
refresh at this interval unless user controlled refresh is turned on (refer to “Controller ”
Memory initialization time (minimum). After reset, the controller does not issue any
commands to the memory during this period.
Precharge command period (minimum). The controller does not access the memory
for this period after issuing a precharge command.
Active to read-write time (minimum). The controller does not issue read or write
commands to a bank during this time after issuing an active command.
Auto-refresh command period (minimum). The length of time the controller waits
before doing anything else after issuing an auto-refresh command.
Write recovery time (minimum). The controller waits for this time after the end of a
write transaction before issuing a precharge command.
Active to precharge time (minimum). The controller waits for this time after issuing an
active command before issuing a precharge command to the same bank.
Load mode register command period (minimum). The controller waits for this time
after issuing a load mode register command before issuing any other commands.
Write to read command delay (minimum). The controller waits for this time after the
end of a write command before issuing a subsequent read command to the same
bank. This timing parameter is specified in clock cycles and so has no entry in the
Required column.
Memory Timings
to perform timing analysis.
Table 3–19. Device Datasheet Settings (Part 1 of 2)
Parameter
t DQSQ
t QHS
t DQSCK
t AC
t CK_MAX
t DS
t DH
Units
ps
ps
ps
ps
ps
ps
ps
Description
The maximum DQS to DQ skew; DQS to last DQ valid, per group, per access.
The maximum data hold skew factor.
The access window of DQS from CK/CK#.
The access window of DQ from CK/CK#.
The maximum permitted clock cycle time.
The minimum DQ and DM input setup time relative to DQS.
The minimum DQ and DM input hold time relative to DQS.
? March 2009 Altera Corporation
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