参数资料
| 型号： | IP-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 81/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 初始许可证 |
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A–3
Parameters
Table A–2. Postamble Options (Part 2 of 2)
Parameter
Postamble clock setting
Dedicated clock phase
Number of DQS delay
matching buffers
Range
0 ( clk , rising edge),
90 ( write_clk , falling
edge),
180 ( clk , falling edge)
270 ( write_clk , rising
edge), or
dedicated
0 to 359
0 to 8
Description
Selects which clock to use for the postamble logic: the
system clock, the write clock (a 90 ° advanced version of the
system clock), or a dedicated postamble clock. Also defines
which edge of the chosen clock to use for the postamble
logic. If you select falling edge, the data path automatically
inserts inverters on the clock inputs to the postamble control
registers.
Allows you to enter the phase of the dedicated postamble
clock that is used for timing analysis. IP Toolbench uses this
value to set up the PLL phase shift.
Inserts the chosen number of delay buffers on the undelayed
DQS in Stratix devices. Insert delay buffers when you are
using low frequencies, to ensure that the capture registers
are not disabled too early.
Table A–3. Capture Options
Parameter
Manual capture control
Capture setting
Dedicated clock phase
Range
On or off
0 ( clk , rising edge),
90 ( write_clk , falling
edge),
180 ( clk , falling edge)
270 ( write_clk , rising
edge), or
dedicated
0 to 359
Description
Turn on to specify the details of the clock used for the
capture logic. Otherwise, the details are calculated
Selects which clock to use for the capture logic: the system
clock, the write clock (a 90 ° advanced version of the system
clock), or a dedicated capture clock. Also defines which edge
of the chosen clock to use for the capture logic. If you select
falling edge, the data path automatically inserts inverters on
the clock inputs to the capture registers.
Allows you to enter the phase of the dedicated capture clock
that is used for timing analysis. IP Toolbench uses this value
to set up the PLL phase shift.
? March 2009
Altera Corporation
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