参数资料
| 型号： | IP-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 63/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 初始许可证 |
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Chapter 3: Functional Description
Interfaces & Signals
Figure 3–18. DDR2 SDRAM Device Initialization Timing
3–27
[1]
[2]
[3] [3]
[4]
[5]
[6]
[7]
[7]
[ 8 ]
[9]
clk
ddr_cke
ddr_a
ddr_ba
2 0 3 0 1 0
0
1 0 1 1
ddr_cs_n
0
0
0
0
0
0
0
ddr_ras_n
ddr_cas_n
ddr_we_n
local_init_done
DDR Command
P
L
L
L
L
P
A
A
L
N
L
L
Key:
P = PCH
200 clock cycles
L = LMR
A = ARF
1. The clock enable signal ( CKE ) is asserted 200 μ s after coming out of reset.
2. The controller then waits 400 ns and then issues the first PCH command by setting
the precharge pin, the address bit a[10] or a[8] high. The 400 ns is calculated by
taking the number of clock cycles calculated by the wizard for the 200 μ s delay and
dividing this by 500. If a small initialization time is selected for simulation
purposes, this delay is always at least 1 clock cycle.
3. Two ELMR commands are issued to load extend mode registers 2 and 3 with
zeros.
4. An ELMR command is issued to extend mode register 1 to enable the internal DLL
in the memory devices.
5. An LMR command is issued to set the operating parameters of the memory such
as CAS latency and burst length. This LMR command is also used to reset the
internal memory device DLL.
6. A further PCH command places all the banks in their idle state.
7. Two ARF commands must follow the PCH command.
8. A final LMR command is issued to program the operating parameters without
resetting the DLL.
9. 200 clock cycles after step 5 , two ELMR commands are issued to set the memory
device off-chip driver (OCD) impedance to the default setting.
The DDR2 SDRAM controller asserts the local_init_done signal, which shows
that it has initialized the memory devices.
? March 2009
Altera Corporation
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