参数资料
| 型号： | IP-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 34/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 初始许可证 |
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2–24
Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
Once compilation is complete, the auto_verify_ddr_timing.tcl script automatically
calls the verify timing script for each instance of the controller in your design. The
post-compilation timing analysis results are displayed in the Quartus II processing
messages tab and are written to the <variation name> _post_summary.txt file in your
project directory.
To prevent the verify timing script from running, turn off Automatically run verify
timing script in the wizard. To manually prevent the script from running, open a
Quartus II Tcl Console window and enter the following command:
set_global_assignment -name POST_FLOW_SCRIPT_FILE -remove
The results show how much slack you have for each of the various timing
requirements—negative slack means that you are not meeting timing. The Message
window shows various timing margins for your design.
If the verify timing script reports that your design meets timing, you have
successfully generated and implemented your DDR or DDR2 SDRAM Controller.
If the timing does not reach your requirements, adjust the resynchronization and
postamble clock phases on the IP Toolbench Manual Timings tab (refer to
To view the constraints in the Quartus II Assignment Editor, click Assignment Editor
(Assignments menu).
1
If you have “?” characters in the Quartus II Assignment Editor, the
Quartus II software cannot find the entity to which it is applying the
constraints, probably because of a hierarchy mismatch. Either edit the
constraints script, or enter the correct hierarchy path in the Hierarchy tab
(refer to step 24 on page 2–13 ).
f
Program a Device
After you have compiled the example design, you can perform gate-level simulation
(refer to “Simulate the Example Design” on page 2–17 ) or program your targeted
Altera device to verify the example design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the DDR or
DDR2 SDRAM controller MegaCore function before you purchase a license.
OpenCore Plus evaluation allows you to generate an IP functional simulation model,
and produce a time-limited programming file.
f
For more information on OpenCore Plus hardware evaluation using the DDR or
Implement Your Design
In the MegaWizard Plug-In flow, to implement your design based on the example
design, replace the example driver in the example design with your own logic.
? March 2009 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
| IP-VITERBI/SS | IP VITERBI LOW-SPEED |
| IP4220CZ6,125 | IC USB DUAL ESD PROTECT 6TSOP |
| IPA-66-1-600-10.0-A-01-T | CIRC BRKR 10A 2POLE SCREW TERM |
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参数描述 |
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| IPSE.4.62SM600 | 制造商:Banner Engineering 功能描述:FIBER IPSE.4.62SM600 GLASS FIBER (MIN ORDER 50) |
| IPS-EMBEDDED | 功能描述:开发软件 Embedded IP Suite MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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