参数资料
| 型号： | IP-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 60/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 初始许可证 |
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3–24
Chapter 3: Functional Description
Interfaces & Signals
2. The user logic requests a write, a read, and another write request, which are
accepted.
3. The controller asserts the write data request signal to ask the user logic to present
valid write data and byte enables on the next clock edge.
4. The read data from the first read request is returned and marked as valid by the
read data valid signal.
5. The controller again asserts the write data request for the second write request.
6. The read data from the second read request is returned.
User Refresh Control
when the controller issues refreshes to the memory. This feature allows better control
of worst case latency and allows refreshes to be issued in bursts to take advantage of
idle periods.
Figure 3–16. User Refresh Control
clk
reset_n
Local Interface
local_refresh_req
local_refresh_ack
DDR SDRAM Interface
[1]
[2] [3]
[4]
ddr_cs_n
FF
00
FF
00
FF
00
FF
ddr_cke
FF
ddr_a
ddr_ba
0000
0400
0
0000
DDR Command
NOP
PCH NOP ARF
NOP
ARF
NOP
ddr_ras_n
ddr_cas_n
ddr_we_n
(1) DDR Command shows the command that the command signals are issuing.
1. The user logic asserts the refresh request signal to indicate to the controller that it
should perform a refresh. The state of the read and write requests signal does not
matter as the controller gives priority to the refresh request (although it completes
any currently active reads or writes).
2. The controller asserts the refresh acknowledge signal to indicate that it has issued
a refresh. This signal is still available even if the user refresh control option is not
switched on, allowing the user logic to keep track of when the controller is issuing
refreshes.
3. The user logic keeps the refresh request signal asserted to indicate that it wishes to
perform another refresh request.
The controller again asserts the refresh acknowledge signal to indicate that it has
issued a refresh. At this point the user logic deasserts the refresh request signal and
the controller continues with the reads and writes in its buffers.
? March 2009 Altera Corporation
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