参数资料
型号: IP-SDRAM/DDR2
厂商: Altera
文件页数: 5/106页
文件大小: 0K
描述: IP DDR2 SDRAM CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: DDR2 SDRAM 控制器
许可证: 初始许可证
1. About This Compiler
Release Information
Table 1–1 provides information about this release of the DDR and DDR2 SDRAM
Controller Compiler.
Table 1–1. DDR & DDR2 SDRAM Controller Release Information
Version
Release Date
Ordering Codes
Product IDs
Vendor ID
Item
Description
9.0
March 2009
IP-SDRAM/DDR (DDR SDRAM)
IP-SDRAM/DDR2 (DDR2 SDRAM)
0055 (DDR SDRAM)
00A7 (DDR2 SDRAM)
00A8 (common library)
6AF7
Device Family Support
MegaCore ? functions provide either full or preliminary support for target Altera ?
device families, as described below:
Full support means the MegaCore function meets all functional and timing
requirements for the device family and may be used in production designs
Preliminary support means the MegaCore function meets all functional
requirements, but may still be undergoing timing analysis for the device family; it
may be used in production designs with caution
Table 1–2 shows the level of support offered by the DDR and DDR2 SDRAM
Controller Compiler to each of the Altera device families.
Table 1–2. Device Family Support (Part 1 of 2)
Support
Device Family
DDR SDRAM
DDR2 SDRAM
Cyclone
?
Full
No support
HardCopy II
Cyclone II
?
Stratix ?
Stratix GX
Stratix II (1)
Stratix II GX
Full
Preliminary
Full
Full
Full
Full
Full
Preliminary
No support
No support
Full
Full
March 2009
Altera Corporation
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