参数资料
| 型号： | IP-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 76/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 初始许可证 |
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3–40
Chapter 3: Functional Description
Parameters
Project Settings
Table 3–22. Example Design Options
Parameter
Update the example design
file that instantiates the
controller variation
Automatically apply
Description
When this option is turned on, IP Toolbench parses and updates the example design file. It
only updates sections that are between the following markers:
<<START MEGAWIZARD INSERT <tagname>
<<END MEGAWIZARD INSERT <tagname>
If you edit the example design file, ensure that your changes are outside of the markers or
remove the markers. Once you remove the markers, you must keep the file updated, because
IP Toolbench can no longer update the file.
When you turn on this option, IP Toolbench updates the example testbench and the ModelSim
simulation script.
When this option is turned on, the next time you compile, the Quartus II software
datapath-specific contraints automatically runs the add constraints script. Turn off this option if you do not want the script
to the Quartus II project
Automatically verify
datapath-specific timing in
the Quartus II project
Update the example design
PLLs
to run automatically
When this option is turned on, after every compilation the Quartus II software automatically
runs the verify timing script. Turn off this option if you do not want the script to run
automatically.
When this option is turned on, IP Toolbench automatically overwrites the PLLs.Turn off this
option, if you do not want the wizard to overwrite the system PLL or the optional fed-back
PLL.
Table 3–23. Variation Path Options
Parameter
Enable hierarchy control
Hierarchy path to your
custom variation
Description
The constraints script analyzes your design, to automatically extract the hierarchy to your
variation. To prevent the constraints script analyzing your design, turn on Enable hierarchy
control , and enter the correct hierarchy path to your datapath.
The hierarchy path is the path to your DDR or DDR2 SDRAM datapath, minus the top-level
name. The hierarchy entered in the wizard must match your design, because the constraints
and timing scripts rely on this path for correct operation.
Table 3–24. Device Pin Prefixes & Names Options
Parameter
Pin name of the clock
driving the memory (+)
Pin name of the clock
driving the memory (–)
Pin name of fed-back clock
input
Pin prefix all pins on the
devices with
Description
The suggested clk_to_sdram pin name, which you may edit, but must end in [0] .
The suggested clk_to_sdram_n pin name, which you may edit, but must end in [0] .
The suggested fedback_clock_in pin name, which you may edit.
This string is used to prefix the pin names for the FPGA pins connected to the DDR or DDR2
SDRAM.
? March 2009 Altera Corporation
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| IPSE.4.33SM600 | 制造商:Banner Engineering 功能描述:FIBER IPSE.4.33SM600 GLASS FIBER (MIN ORDER 50) |
| IPSE.4.62SM600 | 制造商:Banner Engineering 功能描述:FIBER IPSE.4.62SM600 GLASS FIBER (MIN ORDER 50) |
| IPS-EMBEDDED | 功能描述:开发软件 Embedded IP Suite MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPS-EVAL-EH-01 | 功能描述:ENERGY HARVESTING BOARD RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:THINERGY® 标准包装:1 系列:- 主要目的:数字电位器 嵌入式:- 已用 IC / 零件:AD5258 主要属性:- 次要属性:- 已供物品:板 相关产品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP |
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