参数资料
| 型号： | IP-SDRAM/DDR2 |
| 厂商： | Altera |
| 文件页数： | 17/106页 |
| 文件大小： | 0K |
| 描述： | IP DDR2 SDRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | DDR2 SDRAM 控制器 |
| 许可证： | 初始许可证 |
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Chapter 2: Getting Started
2–7
SOPC Builder Design Flow
Edit the PLL
The IP Toolbench-generated example design includes a PLL, which has an input to
output clock ratio of 1:1 and a clock frequency that you entered in IP Toolbench. In
addition, IP Toolbench correctly sets all the phase offsets of all the relevant clock
outputs for your design. You can edit the PLL input clock to make it conform to your
system requirements. If you re-run IP Toolbench, it does not overwrite this PLL, if
you turn off Automatically generate the PLL , so your edits are not lost.
1
f
f
1
If you turn on Use fed-back clock for resynchronization , IP Toolbench generates a
second PLL—the fed-back PLL. You need not edit the fed-back PLL.
To edit the example PLL, follow these steps:
1. Choose MegaWizard Plug-In Manager (Tools menu).
2. Select Edit an existing custom megafunction variation and click Next .
3. In your Quartus II project directory, for VHDL choose ddr_pll_ <device name> .vhd ;
for Verilog HDL choose ddr_pll_ <device name> .v .
4. Click Next .
5. Edit the PLL parameters in the ALTPLL MegaWizard Plug-In Manager.
For more information on the ALTPLL megafunction, refer to the Quartus II Help or
click Documentation in the ALTPLL MegaWizard Plug-In Manager.
Compile & Perform Timing Analysis
Before the Quartus II software compiles the SOPC Builder design, it runs the IP
Toolbench-generated Tcl constraints script, auto_add_constraints.tcl .
The auto_add_constraints.tcl script calls the add_constraints_for_ <variation
name> .tcl script for each variation in your design. The add_constraints_for_ <variation
name> .tcl script checks for any previously added constraints specific to that variation,
removes them, and then adds constraints for that variation.
The constraints script analyzes and elaborates your design, to automatically extract
the hierarchy to your variation. To prevent the constraints script analyzing and
elaborating your design, turn on Enable hierarchy control in the wizard, and enter
the correct hierarchy path to your datapath (refer to step 24 on page 2–13 ).
When the constraints script runs, it creates another script,
remove_constraints_for_ <variation name> .tcl , which can be used to remove the
constraints from your design.
Click Start Compilation (Processing menu), to run the add constraints scripts,
compile the design, and perform timing analysis.
When the compilation is complete, the Quartus II processing message tab displays the
post-compilation timing analysis results. The results are also written to the <variation
name> _post_summary.txt file in your project directory.
? March 2009
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-SLITE2 | IP SERIALLITE II |
| IP-SRAM/QDRII | IP QDRII SRAM CONTROLLER |
| IP-VITERBI/SS | IP VITERBI LOW-SPEED |
| IP4220CZ6,125 | IC USB DUAL ESD PROTECT 6TSOP |
| IPA-66-1-600-10.0-A-01-T | CIRC BRKR 10A 2POLE SCREW TERM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPSE.4.33SM600 | 制造商:Banner Engineering 功能描述:FIBER IPSE.4.33SM600 GLASS FIBER (MIN ORDER 50) |
| IPSE.4.62SM600 | 制造商:Banner Engineering 功能描述:FIBER IPSE.4.62SM600 GLASS FIBER (MIN ORDER 50) |
| IPS-EMBEDDED | 功能描述:开发软件 Embedded IP Suite MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPS-EVAL-EH-01 | 功能描述:ENERGY HARVESTING BOARD RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:THINERGY® 标准包装:1 系列:- 主要目的:数字电位器 嵌入式:- 已用 IC / 零件:AD5258 主要属性:- 次要属性:- 已供物品:板 相关产品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP |
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