参数资料
型号: PI7C8154BNAE
厂商: Pericom
文件页数: 100/114页
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
标准包装: 27
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 304-BBGA
供应商设备封装: 304-PBGA(31x31)
包装: 管件
安装类型: 表面贴装
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 86 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
31-28
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
14.1.30
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
1
Memory Write
Disconnect
Control
R/W
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
3:2
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
4
Secondary Bus
Prefetch Disable
R/W
Controls the bridge’s ability to prefetch during upstream memory read
transactions
0: Bridge prefetches and does not forward byte enable bits during
upstream memory read transactions.
1: Bridge requests only 1 DWORD from the target and forwards read
byte enable bits during upstream memory reads.
Reset to 0
5
Live Insertion
Mode
R/W
Enables control of transaction forwarding
0: GPIO[3] has no effect on the I/O, memory, and master enable bits
1: If GPIO[3] is set to input only, this bit enables GPIO[3] to mask the
I/O enable, memory enable, and master enable bits to 0. These bits are
masked when GPIO[3] is driven HIGH. As a result, PI7C8154 stops
accepting I/O and memory transactions.
Reset to 0
7:6
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
8
Chip Reset
R/WR
Controls the chip and secondary bus reset.
0: Bridge is ready for operation
1: Causes Bridge to perform a chip reset
15:9
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
14.1.31
ARBITER CONTROL REGISTER – OFFSET 40h
Bit
Function
Type
Description
24:16
Arbiter Control
R/W
Each bit controls whether a secondary bus master is assigned to the high
priority group or the low priority group.
Bits [24:16] correspond to request inputs S_REQ[8:0]
0: low priority
1: high priority
Reset to 0
25
Priority of
Secondary
Interface
R/W
Controls whether the secondary interface of the bridge is in the high
priority group or the low priority group.
0: low priority
1: high priority
Reset to 1
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