- 您现在的位置：买卖IC网 > PDF目录11720 > PI7C8154BNAE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF资料下载
参数资料
| 型号： | PI7C8154BNAE |
| 厂商： | Pericom |
| 文件页数： | 93/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页当前第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 8 of 112
JUNE 2008 REVISION 1.1
14.1.26
CAPABILITY POINTER REGISTER – OFFSET 34h ...............................................................84
14.1.27
INTERRUPT LINE REGISTER – OFFSET 3Ch .......................................................................84
14.1.28
INTERRUPT PIN REGISTER – OFFSET 3Ch .........................................................................84
14.1.29
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................................84
14.1.30
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h................................................86
14.1.31
ARBITER CONTROL REGISTER – OFFSET 40h....................................................................86
14.1.32
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h.....................................................87
14.1.33
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h..............................................88
14.1.34
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch..........88
14.1.35
HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch...............................................88
14.1.36
EEPROM AUTOLOAD CONTROL / STATUS REGISTER – OFFSET 50h .............................89
14.1.37
EEPROM ADDRESS / CONTROL REGISTER – OFFSET 54h ...............................................89
14.1.38
EEPROM DATA REGISTER – OFFSET 54h ...........................................................................89
14.1.39
UPSTREAM (S TO P) MEMORY BASE ADDRESS REGISTER – OFFSET 58h .....................90
14.1.40
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS REGISTER – OFFSET 58h ....................90
14.1.41
UPSTREAM (S TO P) MEMORY BASE ADDRESS UPPER 32-BIT REGISTER – OFFSET
5Ch
...................................................................................................................................................90
14.1.42
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS UPPER 32-BIT REGISTER – OFFSET
60h
...................................................................................................................................................90
14.1.43
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h.........................................................90
14.1.44
GPIO DATA AND CONTROL REGISTER – OFFSET 64h ......................................................92
14.1.45
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h...............................................92
14.1.46
P_SERR# STATUS REGISTER – OFFSET 68h ........................................................................94
14.1.47
PORT OPTION REGISTER – OFFSET 74h .............................................................................94
14.1.48
SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h...........................96
14.1.49
PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h.................................96
14.1.50
CAPABILITY ID REGISTER – OFFSET B0h ...........................................................................96
14.1.51
NEXT POINTER REGISTER – OFFSET B0h...........................................................................96
14.1.52
SLOT NUMBER REGISTER – OFFSET B0h ...........................................................................96
14.1.53
CHASSIS NUMBER REGISTER – OFFSET B0h .....................................................................97
14.1.54
CAPABILITY ID REGISTER – OFFSET DCh..........................................................................97
14.1.55
NEXT ITEM POINTER REGISTER – OFFSET DCh ...............................................................97
14.1.56
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh .................................97
14.1.57
POWER MANAGEMENT DATA REGISTER – OFFSET E0h..................................................97
14.1.58
PPB SUPPORT EXTENSIONS REGISTER – OFFSET E0h ....................................................98
14.1.59
DATA REGISTER – OFFSET E0h............................................................................................98
14.1.60
CAPABILITY ID REGISTER – OFFSET E4h ...........................................................................98
14.1.61
NEXT POINTER REGISTER – OFFSET E4h...........................................................................98
14.1.62
HOT SWAP CONTROL AND STATUS REGISTER – OFFSET E4h ........................................98
14.1.63
CAPABILITY ID REGISTER – OFFSET E8h ...........................................................................99
14.1.64
NEXT POINTER REGISTER – OFFSET E8h...........................................................................99
14.1.65
VPD REGISTER – OFFSET E8h ..............................................................................................99
14.1.66
VPD DATA REGISTER – OFFSET ECh ..................................................................................99
15
BRIDGE BEHAVIOR .............................................................................................................................100
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES...................................................................100
15.2
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ........................................100
15.2.1
MASTER ABORT ....................................................................................................................100
15.2.2
PARITY AND ERROR REPORTING ......................................................................................100
15.2.3
REPORTING PARITY ERRORS .............................................................................................101
15.2.4
SECONDARY IDSEL MAPPING............................................................................................101
16
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .........................................................................101
16.1
BOUNDARY SCAN ARCHITECTURE .........................................................................................101
相关PDF资料 |
PDF描述 |
|---|---|
| ADM1025AARQ | IC MONITOR SYS/VOLT 5CH 16QSOP |
| ADUC832BCPZ | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 31-10 | BNC FRONT MOUNT RECEPT |
| D38999/20JD97SN | CONN RCPT 12POS WALL MNT W/SCKT |
| ADUC848BSZ62-5 | IC FLASH MCU W/16BIT ADC 52MQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
发布紧急采购，3分钟左右您将得到回复。