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| 型号： | PI7C8154BNAE |
| 厂商： | Pericom |
| 文件页数： | 25/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 18 of 112
JUNE 2008 REVISION 1.1
Name
Pin #
Type
Description
S_CLKIN
J4
I
Secondary Clock Input: Provides timing for all
transactions on the secondary interface.
S_CLKOUT[9:0]
P1, P2, P3, N1, N3, M2,
M1, M3, L3, L2
O
Secondary Clock Output: Provides secondary
clocks phase synchronous with the P_CLK.
When these clocks are used, one of the clock
outputs must be fed back to S_CLKIN. Unused
outputs may be disabled by:
1. Writing the secondary clock disable bits in the
configuration space
2. Using the serial disable mask using the GPIO pins
and MSK_IN
3. Terminating them electrically.
ASYNC_SEL#
AB1
I
Asynchronous Mode Enable: Enables
asynchronous mode for the bridge.
0: Secondary bus clock outputs (S_CLKOUT[9:0])
will use the clock signal from ASYNC_CLKIN
input instead of the P_CLK.
1: Secondary bus clock outputs (S_CLKOUT[9:0])
will use the P_CLK input for synchronous
operation.
ASYNC_CLKIN
AB2
I
Asynchronous Mode Clock: External clock input
used to generate the secondary clock outputs
(S_CLKOUT[9:0]) when enabled by
ASYNC_SEL#
1.2.6
MISCELLANEOUS SIGNALS
Name
Pin #
Type
Description
MSK_IN
R21
I
Secondary Clock Disable Serial Input: This pin is
used by bridge to disable secondary clock outputs.
The serial stream is received by MSK_IN, starting
when P_RESET is detected deasserted and
S_RESET# is detected as being asserted. The serial
data is used for selectively disabling secondary
clock outputs and is shifted into the secondary clock
control configuration register. This pin can be tied
LOW to enable all secondary clock outputs or tied
HIGH to drive all the secondary clock outputs
HIGH.
P_VIO
R20
I
Primary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the primary bus.
P_VIO must be tied to 3.3V only when all devices
on the primary bus use 3.3V signaling. Otherwise,
P_VIO is tied to 5V.
S_VIO
N22
I
Secondary I/O Voltage: This pin is used to
determine either 3.3V or 5V signaling on the
secondary bus. S_VIO must be tied to 3.3V only
when all devices on the secondary bus use 3.3V
signaling. Otherwise, S_VIO is tied to 5V.
BPCCE
R4
I
Bus/Power Clock Control Management Pin:
When this pin is tied HIGH and the bridge is placed
in the D2 or D3HOT power state, it enables the bridge
to place the secondary bus in the B2 power state.
The secondary clocks are disabled and driven to 0.
When this pin is tied LOW, there is no effect on the
secondary bus clocks when the bridge enters the D2
or D3HOT power state.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
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