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参数资料
| 型号： | PI7C8154BNAE |
| 厂商： | Pericom |
| 文件页数： | 70/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 59 of 114
JUNE 2008 REVISION 1.1
Secondary
Detected Parity
Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
0
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
Note: x=don’t care
Table 5-3 shows setting data parity detected bit in the primary interface’s status register. This bit is
set under the following conditions:
PI7C8154B must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary interface,
must be set.
The P_PERR# signal is detected asserted or a parity error is detected on the primary bus.
Table 5-3 SETTING THE PRIMARY INTERFACE DATA PARITY DETECTED BIT (bit
24 of offset 04h)
Primary Data
Parity Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary / Secondary Parity
Error Response Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
1 / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
1 / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
1 / x
0
Delayed Write
Upstream
Secondary
x / x
Note: x=don’t care
Table 5-4 shows setting the data parity detected bit in the status register of secondary interface.
This bit is set under the following conditions:
The PI7C8154B must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.
Table 5-4 SETTING THE SECONDARY INTERFACE DATA PARITY DETECTED BIT
Secondary
Detected Parity
Detected Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary / Secondary Parity
Error Response Bits
0
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / 1
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / 1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
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