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参数资料
| 型号： | PI7C8154BNAE |
| 厂商： | Pericom |
| 文件页数： | 34/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 26 of 112
JUNE 2008 REVISION 1.1
PI7C8154B ends the transaction on the target bus when one of the following conditions is met:
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (PI7C8154B starts another transaction to
deliver the rest of the write data).
The target returns a target abort (PI7C8154B discards remaining write data).
The master latency timer expires, and PI7C8154B no longer has the target bus grant
(PI7C8154B starts another transaction to deliver remaining write data).
Section 2.11.3.2 provides detailed information about how PI7C8154B responds to target
termination during posted write transactions.
2.6.2
MEMORY WRITE AND INVALIDATE
Posted write forwarding is used for Memory Write and Invalidate transactions.
The PI7C8154B disconnects Memory Write and Invalidate commands at aligned cache line
boundaries. The cache line size value in the cache line size register gives the number of DWORD
in a cache line.
If the value in the cache line size register does meet the memory write and invalidate conditions,
the PI7C8154B returns a target disconnect to the initiator on a cache line boundary.
2.6.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding is used for I/O write transactions and Type 1 configuration write
transactions.
A delayed write transaction guarantees that the actual target response is returned back to the
initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a
single DWORD data transfer.
When a write transaction is first detected on the initiator bus, and PI7C8154B forwards it as a
delayed transaction, PI7C8154B claims the access by asserting DEVSEL# and returns a target retry
to the initiator. During the address phase, PI7C8154B samples the bus command, address, and
address parity one cycle later. After IRDY# is asserted, PI7C8154B also samples the first data
DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction
queue. The transaction is queued only if no other existing delayed transactions have the same
address and command, and if the delayed transaction queue is not full. When the delayed write
transaction moves to the head of the delayed transaction queue and all ordering constraints with
posted data are satisfied. The PI7C8154B initiates the transaction on the target bus. PI7C8154B
transfers the write data to the target. If PI7C8154B receives a target retry in response to the write
transaction on the target bus, it continues to repeat the write transaction until the data transfer is
completed, or until an error condition is encountered.
If PI7C8154B is unable to deliver write data after 224 (default) or 232 (maximum) attempts,
PI7C8154B will report a system error. PI7C8154B also asserts P_SERR# if the primary SERR#
enable bit is set in the command register. See Section 5.4 for information on the assertion of
P_SERR#. When the initiator repeats the same write transaction (same command, address, byte
enable bits, and data), and the completed delayed transaction is at the head of the queue, the
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
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