参数资料
型号: PI7C8154BNAE
厂商: Pericom
文件页数: 47/114页
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
标准包装: 27
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 304-BBGA
供应商设备封装: 304-PBGA(31x31)
包装: 管件
安装类型: 表面贴装
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 38 of 112
JUNE 2008 REVISION 1.1
the same cycle in which FRAME# deasserts. If FRAME# is already deasserted, IRDY# can be
deasserted on the next clock cycle following detection of the master abort condition.
The target can terminate transactions with one of the following types of termination:
Normal termination
TRDY# and DEVSEL# asserted in conjunction with FRAME# deasserted and IRDY# asserted.
Target retry
STOP# and DEVSEL# asserted with TRDY# deasserted during the first data phase. No data
transfers occur during the transaction. This transaction must be repeated.
Target disconnect with data transfer
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the
transaction.
Target disconnect without data transfer
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been
made, indicating that no more data transfers will be made during this transaction.
Target abort
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to
complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction
before the target abort is signaled.
2.11.1
MASTER TERMINATION INITIATED BY PI7C8154B
PI7C8154B, as an initiator, uses normal termination if DEVSEL# is returned by target within five
clock cycles of PI7C8154B’s assertion of FRAME# on the target bus. As an initiator, PI7C8154B
terminates a transaction when the following conditions are met:
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data buffers
to the target.
For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the
master latency timer expires and the PI7C8154B’s bus grant is de-asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
If PI7C8154B is delivering posted write data when it terminates the transaction because the master
latency timer expires, it initiates another transaction to deliver the remaining write data. The
address of the transaction is updated to reflect the address of the current DWORD to be delivered.
If PI7C8154B is pre-fetching read data when it terminates the transaction because the master
latency timer expires, it does not repeat the transaction to obtain more data.
2.11.2
MASTER ABORT RECEIVED BY PI7C8154B
If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by
the target within five clock cycles of the assertion of FRAME#, PI7C8154B terminates the
相关PDF资料
PDF描述
ADM1025AARQ IC MONITOR SYS/VOLT 5CH 16QSOP
ADUC832BCPZ IC MCU 62K FLASH ADC/DAC 56LFCSP
31-10 BNC FRONT MOUNT RECEPT
D38999/20JD97SN CONN RCPT 12POS WALL MNT W/SCKT
ADUC848BSZ62-5 IC FLASH MCU W/16BIT ADC 52MQFP
相关代理商/技术参数
参数描述
PI7C8154BNAE-80 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray
PI7C8154BNAI 制造商:Pericom Semiconductor Corporation 功能描述:
PI7C8154BNAIE 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray
PI7C8154EVB 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V
PI7C8154NA-33 制造商:PERICOM 功能描述: