![](http://datasheet.mmic.net.cn/Pericom/PI7C8154BNAIE_datasheet_99378/PI7C8154BNAIE_94.png)
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 94 of 114
JUNE 2008 REVISION 1.1
14.1.46
P_SERR# STATUS REGISTER – OFFSET 68h
Bit
Function
Type
Description
16
Address Parity
Error
R/WC
1: Signal P_SERR# was asserted because an address parity error was
detected on P or S bus.
Reset to 0
17
Posted Write
Data Parity Error
R/WC
1: Signal P_SERR# was asserted because a posted write data parity error
was detected on the target bus.
Reset to 0
18
Posted Write
Non-delivery
R/WC
1: Signal P_SERR# was asserted because the bridge was unable to deliver
post memory write data to the target after 224 attempts.
Reset to 0
19
Target Abort
during Posted
Write
R/WC
1: Signal P_SERR# was asserted because the bridge received a target
abort when delivering post memory write data.
Reset to 0.
20
Master Abort
during Posted
Write
R/WC
1: Signal P_SERR# was asserted because the bridge received a master
abort when attempting to deliver post memory write data
Reset to 0.
21
Delayed Write
Non-delivery
R/WC
1: Signal P_SERR# was asserted because the bridge was unable to deliver
delayed write data after 224 attempts.
Reset to 0
22
Delayed Read –
No Data from
Target
R/WC
1: Signal P_SERR# was asserted because the bridge was unable to read
any data from the target after 224 attempts.
Reset to 0.
23
Delayed
Transaction
Master Timeout
R/WC
1: Signal P_SERR# was asserted because a master did not repeat a read or
write transaction before master timeout.
Reset to 0.
31:24
Reserved
R/O
Returns 0 when read. Reset to 0
14.1.47
PORT OPTION REGISTER – OFFSET 74h
Bit
Function
Type
Description
0
Reserved
R/O
Returns 0 when read. Reset to 0.
1
Primary Memory
Read Command
Alias Enable
R/W
0: exact matching for non-posted memory write retry cycles from initiator
on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry cycles
from the initiator on the primary interface
Reset to 1
2
Primary Memory
Write Command
Alias Enable
R/W
Reserved
Reset to 0
3
Secondary
Memory Read
Command Alias
Enable
R/W
0: exact matching for memory read retry cycles from initiator on the
secondary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry cycles
from initiator on the secondary interface
Reset to 1