参数资料
型号: PI7C8154BNAE
厂商: Pericom
文件页数: 97/114页
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
标准包装: 27
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 304-BBGA
供应商设备封装: 304-PBGA(31x31)
包装: 管件
安装类型: 表面贴装
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 83 of 114
JUNE 2008 REVISION 1.1
14.1.21
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET
24h
Bit
Function
Type
Description
19:16
64-bit addressing
R/O
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
31:20
Prefetchable
Memory Limit
Address [31:20]
R/W
Defines the top address of an address range for the bridge to determine
when to forward memory read and write transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20] and are
writable. The lower 20 bits are assumed to be FFFFFh.
14.1.22
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
Bit
Function
Type
Description
31:0
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
R/W
Defines the upper 32-bits of a 64-bit bottom address of an address range
for the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
14.1.23
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
Bit
Function
Type
Description
31:0
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
R/W
Defines the upper 32-bits of a 64-bit top address of an address range for
the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
14.1.24
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
Function
Type
Description
15:0
I/O Base
Address, Upper
16-bits [31:16]
R/W
Defines the upper 16-bits of a 32-bit bottom address of an address range
for the bridge to determine when to forward I/O transactions from one
interface to the other.
Reset to 0
14.1.25
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
Function
Type
Description
31:16
I/O Limit
Address, Upper
16-bits [31:16]
R/W
Defines the upper 16-bits of a 32-bit top address of an address range for
the bridge to determine when to forward I/O transactions from one
interface to the other.
Reset to 0
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