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参数资料
| 型号： | PI7C8154BNAE |
| 厂商： | Pericom |
| 文件页数： | 95/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 81 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
7:4
I/O Base Address
[15:12]
R/W
Defines the bottom address of the I/O address range for the bridge to
determine when to forward I/O transactions from one interface to the
other. The upper 4 bits correspond to address bits [15:12] and are
writable. The lower 12 bits corresponding to address bits [11:0] are
assumed to be 0. The upper 16 bits corresponding to address bits [31:16]
are defined in the I/O base address upper 16 bits address register
Reset to 0
14.1.16
I/O LIMIT REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
9:8
32-bit Indicator
R/O
Read as 01h to indicate 32-bit I/O addressing
11:10
Reserved
R/O
Returns 00 when read. Reset to 00
15:12
I/O Limit
Address
[15:12]
R/W
Defines the top address of the I/O address range for the bridge to
determine when to forward I/O transactions from one interface to the
other. The upper 4 bits correspond to address bits [15:12] and are
writable. The lower 12 bits corresponding to address bits [11:0] are
assumed to be FFFh. The upper 16 bits corresponding to address bits
[31:16] are defined in the I/O limit address upper 16 bits address register
Reset to 0
14.1.17
SECONDARY STATUS REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
20:16
Reserved
R/O
Reset to 0
21
66MHz Capable
R/O
Set to 1 to enable 66MHz operation on the secondary interface
Reset to 1
22
Reserved
R/O
Reset to 0
23
Fast Back-to-
Back Capable
R/O
Set to 1 to indicate bridge is capable of decoding fast back-to-back
transactions on the secondary interface to different targets
Reset to 1
24
Data Parity Error
Detected
R/WC
Set to 1 when S_PERR# is asserted and bit 6 of command register is set
Reset to 0
26:25
DEVSEL#
timing
R/O
DEVSEL# timing (medium decoding)
01: medium DEVSEL# decoding
Reset to 01
27
Signaled Target
Abort
R/WC
Set to 1 (by a target device) whenever a target abort cycle occurs on its
secondary interface
Reset to 0
28
Received Target
Abort
R/WC
Set to 1 (by a master device) whenever transactions on its secondary
interface are terminated with target abort
Reset to 0
29
Received Master
Abort
R/WC
Set to 1 (by a master) when transactions on its secondary interface are
terminated with Master Abort
Reset to 0
30
Received System
Error
R/WC
Set to 1 when S_SERR# is asserted
Reset to 0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
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