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| 型号： | PI7C8154BNAE |
| 厂商： | Pericom |
| 文件页数： | 83/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 70 of 114
JUNE 2008 REVISION 1.1
After the shift operation is complete, the bridge tri-states the GPIO signals and deasserts
S_RESET#. PI7C8154B then ignores MSK_IN. Control of the GPIO signal now reverts to
PI7C8154B GPIO control registers. The clock disable mask can be modified subsequently through
a configuration write command to the secondary clock control register in device-specific
configuration space.
8.3
LIVE INSERTION
The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction
forwarding.
To enable live insertion mode, the live insertion mode bit in the chip control register must be set to
1, and the output enable control for GPIO[3] must be set to input only in the GPIO output enable
control register. When live insertion mode is enabled, whenever GPIO[3] is driven to a value of 1,
the I/O enable, the memory enable, and the master enable bits are internally masked to 0. This
means that, as a target, PI7C8154B no longer accepts any I/O or memory transactions, on either
interface. When read, the register bits still reflect the value originally written by a configuration
write command; when GPIO[3] is deasserted, the internal enable bits return to their original value
(as they appear when read from the command register). When this mode is enabled, as a master,
PI7C8154B completes any posted write or delayed request transactions that have already been
queued.
Delayed completion transactions are not returned to the master in this mode because the bridge is
not responding to any I/O or memory transactions during this time. PI7C8154B continues to accept
Type 0 configuration transactions in live insertion mode. Once live insertion mode brings the
bridge to a halt and queued transactions are completed, the secondary reset bit in the bridge control
register can be used to assert S_RESET#, if desired, to reset and tri-state secondary bus devices,
and to enable any live insertion hardware.
9
EEPROM INTERFACE
The EEPROM interface consists of three pins: EECLK (EEPROM clock output), EEPD
(EEPROM bi-directional serial data), and EE_EN# (EEPROM enable on a LOW input). The
bridge may control an ISSI IS24C02 or compatible part, which is organized into 256x8 bits. The
EEPROM is used to initialize a select number of registers. This is accomplished after P_RESET#
is deasserted, at which time the data from the EEPROM will be loaded. The EEPROM interface is
organized into a 16-bit base, and the bridge supplies a 7-bit EEPROM word address. The bridge
does not control the EEPROM address input. It can only access the EEPROM with address input
set to 0.
9.1
AUTO MODE EEPROM ACCESS
The bridge may access the EEPROM in a WORD format by utilizing the auto mode through a
hardware sequencer. The EEPROM start control, address, and read/write commands can be
accessed through the configuration register. Before each access, the software should check the
Start EEPROM bit before issuing the next start.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
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