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参数资料
型号： PI7C8154BNAE
厂商： Pericom
文件页数： 72/114页
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
标准包装： 27
系列： *
应用： *
接口： *
电源电压： *
封装/外壳： 304-BBGA
供应商设备封装： 304-PBGA（31x31）
包装： 管件
安装类型： 表面贴装
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 60 of 114
JUNE 2008 REVISION 1.1
Secondary
Detected Parity
Detected Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary / Secondary Parity
Error Response Bits
0
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / 1
0
Delayed Write
Upstream
Primary
x / x
0
Delayed Write
Upstream
Secondary
x / x
Note: x=don’t care
Table 5-5 shows assertion of P_PERR#. This signal is set under the following conditions:
PI7C8154B is either the target of a write transaction or the initiator of a read transaction on the
primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8154B detects a data parity error on the primary bus or detects S_PERR# asserted during
the completion phase of a downstream delayed write transaction on the target (secondary) bus.
Table 5-5 ASSERTION OF P_PERR#
P_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
0 (asserted)
Read
Upstream
Primary
1 / x
1
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
1 / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
1 / x
02
Delayed Write
Downstream
Secondary
1 / 1
1
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
Notes: x=don’t care
2
=The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-6 shows assertion of S_PERR# that is set under the following conditions:
PI7C8154B is either the target of a write transaction or the initiator of a read transaction on the
secondary bus.
The parity error response bit must be set in the bridge control register of secondary interface.
PI7C8154B detects a data parity error on the secondary bus or detects P_PERR# asserted
during the completion phase of an upstream delayed write transaction on the target (primary)
bus.
Table 5-6 ASSERTION OF S_PERR#
S_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/ Secondary Parity
Error Response Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
0 (asserted)
Read
Downstream
Secondary
x / 1
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / 1
1
Delayed Write
Downstream
Primary
x / x
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