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参数资料
型号： PI7C8154BNAE
厂商： Pericom
文件页数： 81/114页
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
标准包装： 27
系列： *
应用： *
接口： *
电源电压： *
封装/外壳： 304-BBGA
供应商设备封装： 304-PBGA（31x31）
包装： 管件
安装类型： 表面贴装
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 69 of 114
JUNE 2008 REVISION 1.1
Table 8-1 GPIO OPERATION
GPIO Pin
Operation
GPIO[0]
Shift register clock output at 33MHz max frequency
GPIO[1]
Not used
GPIO[2]
Shift register control
0: Load
1: Shift
GPIO[3]
Not used
The data is input through the dedicated input signal, MSK_IN.
The shift register circuitry is not necessary for correct operation of PI7C8154B. The shift register
can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock outputs or tied
HIGH to force all secondary clock outputs HIGH. Table 8-2 shows the format of the serial stream.
Table 8-2 GPIO SERIAL DATA FORMAT
Bit
Description
S_CLKOUT
[1:0]
Slot 0 PRSNT#[1:0] or device 0
0
[3:2]
Slot 1 PRSNT#[1:0] or device 1
1
[5:4]
Slot 2 PRSNT#[1:0] or device 2
2
[7:6]
Slot 3 PRSNT#[1:0] or device 3
3
[8]
Device 4
4
[9]
Device 5
5
[10]
Device 6
6
[11]
Device 7
7
[12]
Device 8
8
[13]
PI7C8154B S_CLKIN
9
[14]
Reserved
NA
[15]
Reserved
NA
The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control the
S_CLKOUT[3:0] outputs. If one or both of the PRSNT#[1:0] signals are 0, that indicates that a
card is present in the slot and therefore the secondary clock for that slot is not masked. If these
clocks are connected to devices and not to slots, one or both of the bits should be tied low to enable
the clock.
The next 5 bits are the clock mask for devices; each bit enables or disables the clock for one device.
These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1 disables the clock.
Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8154B’s S_CLKIN
input.
If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8154B’s S_CLKIN
input can be rearranged from the assignment shown here. However, it is important that the serial
data stream format match the assignment of S_CLKOUT.
The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits are tied
high to disable their respective secondary clocks because those clocks are not connected to
anything. The next bit is tied LOW because that secondary clock output is connected to the bridge
S_CLKIN input. When the secondary reset signal, S_RESET#, is detected asserted and the primary
reset signal, P_RESET#, is detected deasserted, the bridge drives GPIO[2] LOW for one cycle to
load the clock mask inputs into the shift register. On the next cycle, PI7C8154B drives GPIO[2]
HIGH to perform a shift operation. This shifts the clock mask into MSK_IN; the most significant
bit is shifted in first, and the least significant bit is shifted in last.
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