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参数资料
型号： PI7C8154BNAE
厂商： Pericom
文件页数： 99/114页
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
标准包装： 27
系列： *
应用： *
接口： *
电源电压： *
封装/外壳： 304-BBGA
供应商设备封装： 304-PBGA（31x31）
包装： 管件
安装类型： 表面贴装
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 85 of 114
JUNE 2008 REVISION 1.1
Bit
Function
Type
Description
19
VGA enable
R/W
Controls the bridge’s response to VGA compatible addresses.
0: does not forward VGA compatible memory and I/O addresses from
primary to secondary
1: forward VGA compatible memory and I/O addresses from primary to
secondary regardless of other settings
Reset to 0
20
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
21
Master Abort
Mode
R/W
Control’s bridge’s behavior responding to master aborts on secondary
interface.
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible or by the
assertion of P_SERR# if enabled
Reset to 0
22
Secondary
Interface Reset
R/W
Controls the assertion of S_RESET# signal pin on the secondary interface
0: does not force the assertion of S_RESET# pin
1: forces the assertion of S_RESET#
Reset to 0
23
Fast Back-to-
Back Enable
R/W
Controls bridge’s ability to generate fast back-to-back transactions on the
secondary interface.
0: does not allow fast back-to-back transactions on the secondary
1: enables fast back-to-back transactions on the secondary
Reset to 0
24
Primary Master
Timeout
R/W
Determines the maximum number of PCI clock cycles the bridge waits
for an initiator on the primary interface to repeat a delayed transaction
request.
0: Primary discard timer counts 215 PCI clock cycles.
1: Primary discard timer counts 210 PCI clock cycles.
Reset to 0
25
Secondary
Master Timeout
R/W
Determines the maximum number of PCI clock cycles the bridge waits
for an initiator on the primary interface to repeat a delayed transaction
request.
0: Primary discard timer counts 215 PCI clock cycles.
1: Primary discard timer counts 210 PCI clock cycles.
Reset to 0
26
Master Timeout
Status
R/WC
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
27
Discard Timer
P_SERR# enable
R/W
This bit is set to 1 and P_SERR# is asserted when either the primary
discard timer or the secondary discard timer expire.
0: P_SERR# is not asserted on the primary interface as a result of the
expiration of either the Primary Discard Timer or the Secondary Discard
Timer.
1: P_SERR# is asserted on the primary interface as a result of the
expiration of either the Primary Discard Timer or the Secondary Discard
Timer.
Reset to 0
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相关代理商/技术参数
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