- 您现在的位置：买卖IC网 > PDF目录11720 > PI7C8154BNAE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF资料下载
参数资料
| 型号： | PI7C8154BNAE |
| 厂商： | Pericom |
| 文件页数： | 76/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页当前第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 64 of 114
JUNE 2008 REVISION 1.1
6.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION
The bridge ignores upstream lock and transactions. The bridge will pass these transactions as
normal transactions without lock established.
6.3
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, the bridge must maintain the
lock on the target bus for any subsequent locked transactions until the initiator relinquishes the
lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction of a locked
sequence. On subsequent transactions in the sequence, the target retry has no effect on the status of
the lock signal.
An established target lock is maintained until the initiator relinquishes the lock. The bridge does
not know whether the current transaction is the last one in a sequence of locked transactions until
the initiator de-asserts the LOCK# signal at end of the transaction.
When the last locked transaction is a delayed transaction, the bridge has already completed the
transaction on the target bus. In this example, as soon as the bridge detects that the initiator has
relinquished the LOCK# signal by sampling it in the de-asserted state while FRAME# is de-
asserted, the bridge de-asserts the LOCK# signal on the target bus as soon as possible. Because of
this behavior, LOCK# may not be de-asserted until several cycles after the last locked transaction
has been completed on the target bus. As soon as the bridge has de-asserted LOCK# to indicate the
end of a sequence of locked transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, the bridge de-asserts LOCK# on the
target bus at the end of the transaction because the lock was relinquished at the end of the write
transaction on the initiator bus.
When the bridge receives a target abort or a master abort in response to a locked delayed
transaction, the bridge returns a target abort or a master abort when the initiator repeats the locked
transaction. The initiator must then de-assert LOCK# at the end of the transaction. The bridge sets
the appropriate status bits, flagging the abnormal target termination condition (see Section 2.11).
Normal forwarding of unlocked posted and delayed transactions is resumed.
When PI7C8154B receives a target abort or a master abort in response to a locked posted write
transaction, PI7C8154B cannot pass back that status to the initiator. PI7C8154B asserts SERR# on
the initiator bus when a target abort or a master abort is received during a locked posted write
transaction, if the SERR# enable bit is set in the command register. Signal SERR# is asserted for
the master abort condition if the master abort mode bit is set in the bridge control register (see
Section 5.4).
7
PCI BUS ARBITRATION
The bridge must arbitrate for use of the primary bus when forwarding upstream transactions. Also,
it must arbitrate for use of the secondary bus when forwarding downstream transactions. The
arbiter for the primary bus resides external to the bridge, typically on the motherboard. For the
相关PDF资料 |
PDF描述 |
|---|---|
| ADM1025AARQ | IC MONITOR SYS/VOLT 5CH 16QSOP |
| ADUC832BCPZ | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 31-10 | BNC FRONT MOUNT RECEPT |
| D38999/20JD97SN | CONN RCPT 12POS WALL MNT W/SCKT |
| ADUC848BSZ62-5 | IC FLASH MCU W/16BIT ADC 52MQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
发布紧急采购，3分钟左右您将得到回复。