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参数资料
| 型号： | PI7C8154BNAE |
| 厂商： | Pericom |
| 文件页数： | 78/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 66 of 114
JUNE 2008 REVISION 1.1
Figure 7-1 SECONDARY ARBITER EXAMPLE
Each bus master, including PI7C8154B, can be configured to be in either the low priority group or
the high priority group by setting the corresponding priority bit in the arbiter-control register. The
arbiter-control register is located at offset 40h. Each master has a corresponding bit. If the bit is set
to 1, the master is assigned to the high priority group. If the bit is set to 0, the master is assigned to
the low priority group. If all the masters are assigned to one group, the algorithm defaults to a
straight rotating priority among all the masters. After reset, all external masters are assigned to the
low priority group, and PI7C8154B is assigned to the high priority group. PI7C8154B receives
highest priority on the target bus every other transaction and priority rotates evenly among the
other masters.
Priorities are re-evaluated every time S_FRAME# is asserted at the start of each new transaction on
the secondary PCI bus. From this point until the time that the next transaction starts, the arbiter
asserts the grant signal corresponding to the highest priority request that is asserted. If a grant for a
particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-
asserts the asserted grant signal and asserts the grant corresponding to the new higher priority
request on the next PCI clock cycle. When priorities are re-evaluated, the highest priority is
assigned to the next highest priority master relative to the master that initiated the previous
transaction. The master that initiated the last transaction now has the lowest priority in its group.
If PI7C8154B detects that an initiator has failed to assert S_FRAME# after 16 cycles of both grant
assertion and a secondary idle bus condition, the arbiter de-asserts the grant.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant
signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and asserts the
next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is,
S_FRAME# or S_IRDY# is asserted, the arbiter can be de-asserted one grant and asserted another
grant during the same PCI clock cycle.
7.2.2
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit 31=0).
Time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0) clocks. If the
current master occupies the bus and other masters are waiting, the current master will be preempted
by removing its grant (GNT#) after the next master waits for the time-to-preempt.
m1
m2
m0
m3
m4
m6
m7
m8
B
lpg
m5
lpg:
low priority group
B:
PI7C8154B
Mx:
bus master
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
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