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参数资料
| 型号： | PI7C8154BNAE |
| 厂商： | Pericom |
| 文件页数： | 82/114页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 标准包装： | 27 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 304-BBGA |
| 供应商设备封装： | 304-PBGA（31x31） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 7 of 112
JUNE 2008 REVISION 1.1
7.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER .......................................67
7.2.4
BUS PARKING ..............................................................................................................................67
8
GENERAL PURPOSE I/O INTERFACE ...............................................................................................67
8.1
GPIO CONTROL REGISTERS.........................................................................................................68
8.2
SECONDARY CLOCK CONTROL..................................................................................................68
8.3
LIVE INSERTION .............................................................................................................................70
9
EEPROM INTERFACE............................................................................................................................70
9.1
AUTO MODE EEPROM ACCESS ...................................................................................................70
9.2
EEPROM MODE AT RESET............................................................................................................71
9.3
EEPROM DATA STRUCTURE........................................................................................................71
9.4
EEPROM CONTENT ........................................................................................................................71
10
VITAL PRODUCT DATA (VPD) ............................................................................................................72
11
CLOCKS.....................................................................................................................................................72
11.1
PRIMARY AND SECONDARY CLOCK INPUTS..........................................................................72
11.2
SECONDARY CLOCK OUTPUTS ..................................................................................................72
11.3
ASYNCHRONOUS MODE...............................................................................................................72
12
PCI POWER MANAGEMENT................................................................................................................73
13
RESET.........................................................................................................................................................74
13.1
PRIMARY INTERFACE RESET ......................................................................................................74
13.2
SECONDARY INTERFACE RESET................................................................................................74
13.3
CHIP RESET......................................................................................................................................75
14
CONFIGURATION REGISTERS ...........................................................................................................76
14.1.1
SIGNAL TYPES.........................................................................................................................77
14.1.2
VENDOR ID REGISTER – OFFSET 00h .................................................................................77
14.1.3
DEVICE ID REGISTER – OFFSET 00h ...................................................................................77
14.1.4
COMMAND REGISTER – OFFSET 04h ..................................................................................77
14.1.5
STATUS REGISTER – OFFEST 04h.........................................................................................78
14.1.6
REVISION ID REGISTER – OFFSET 08h................................................................................79
14.1.7
CLASS CODE REGISTER – OFFSET 08h ...............................................................................79
14.1.8
CACHE LINE SIZE REGISTER – OFFSET 0Ch ......................................................................79
14.1.9
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch.......................................................79
14.1.10
HEADER TYPE REGISTER – OFFSET 0Ch............................................................................80
14.1.11
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ............................................................80
14.1.12
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ......................................................80
14.1.13
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ..................................................80
14.1.14
SECONDARY LATENCY TIMER – OFFSET 18h ....................................................................80
14.1.15
I/O BASE REGISTER – OFFSET 1Ch ......................................................................................80
14.1.16
I/O LIMIT REGISTER – OFFSET 1Ch .....................................................................................81
14.1.17
SECONDARY STATUS REGISTER – OFFSET 1Ch ................................................................81
14.1.18
MEMORY BASE REGISTER – OFFSET 20h ...........................................................................82
14.1.19
MEMORY LIMIT REGISTER – OFFSET 20h ..........................................................................82
14.1.20
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ...........................82
14.1.21
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ..........................83
14.1.22
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h83
14.1.23
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch..
...................................................................................................................................................83
14.1.24
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .........................................83
14.1.25
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h........................................83
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外围驱动器与原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8154EVB | 功能描述:界面开发工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
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