RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
95
Register 00AH, 10AH, 20AH, 30AH: Master Diagnostics
Bit
Type
Function
Default
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
R/W
PAYLB
0
Bit 4
R/W
LINELB
0
Bit 3
R/W
RAIS
0
Bit 2
R/W
DDLB
0
Bit 1
R/W
TXMFP
0
Bit 0
R/W
Reserved
0
PAYLB:
The PAYLB bit selects the payload loopback mode, where the received data output from the
RX-ELST is internally connected to the transmit data input of the transmitter. The data read
out of RX-ELST is timed to the transmitter clock, and the transmit frame alignment is used to
synchronize the output frame alignment of RX-ELST. The transmit frame alignment is either
arbitrary (when the TX-ELST is used) or is specified by the BTFP[x] input (when the TX-ELST
is bypassed). During payload loopback, the data on BRPCM[x] is only valid when the
quadrant is configured as a BRCLK[x] master, BRFP[x] master and the RX-ELST is bypassed.
When the RX-ELST is not bypassed, the BRPCM[x] or MVBRD output for the quadrant is
forced to all-ones. During payload loopback in Receive Clock Slave: Full T1/E1 with CCS H-
MVIP mode, the data on CCSBRD remains valid. When PAYLB is set to logic 1, the payload
loopback mode is enabled. When PAYLB is set to logic 0, the loopback mode is disabled. In
T1 mode, if the TDPR is configured to send performance reports from the T1-APRM, this bit
requires two updating cycles before being included in the performance report. Only one of
PAYLB, LINELB, and DDLB can be enabled at any one time.
LINELB:
The LINELB bit selects the line loopback mode, where the recovered data are internally
directed to the digital inputs of the transmit jitter attenuator. The data sent to the TJAT is the
recovered data from the output of the CDRC block. When LINELB is set to logic 1, the line
loopback mode is enabled. When LINELB is set to logic 0, the line loopback mode is
disabled. Note that when line loopback is enabled, to correctly attenuate the jitter on the
receive clock, the contents of the TJAT Reference Clock Divisor and Output Clock Divisor
registers should be programmed to 2FH in T1 or FFH in E1 and the Transmit Timing Options
register should be cleared to all zeros. Only one of PAYLB, LINELB, and DDLB can be
enabled at any one time.